mirror of https://github.com/YosysHQ/yosys.git
e833c6a418
- Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change |
||
|---|---|---|
| .. | ||
| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| pmgen | ||
| proc | ||
| sat | ||
| techmap | ||
| tests | ||