mirror of https://github.com/YosysHQ/yosys.git
102 lines
2.5 KiB
Verilog
102 lines
2.5 KiB
Verilog
///////////////////////////////////////////////////////////////////////////
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// MODULE : counter_tb //
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// TOP MODULE : -- //
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// //
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// PURPOSE : 4-bit up counter test bench //
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// //
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// DESIGNER : Deepak Kumar Tala //
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// //
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// Revision History //
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// //
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// DEVELOPMENT HISTORY : //
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// Rev0.0 : Jan 03, 2003 //
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// Initial Revision //
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// //
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///////////////////////////////////////////////////////////////////////////
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module testbench;
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integer file;
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reg clk = 0, reset = 0, enable = 0;
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wire [3:0] count;
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reg dut_error = 0;
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counter U0 (
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.count (count)
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);
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event reset_enable;
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event terminate_sim;
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initial
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file = $fopen(`outfile);
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always
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#5 clk = !clk;
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initial
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@ (terminate_sim) begin
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$fdisplay (file, "Terminating simulation");
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if (dut_error == 0) begin
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$fdisplay (file, "Simulation Result : PASSED");
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end
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else begin
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$fdisplay (file, "Simulation Result : FAILED");
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end
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$fdisplay (file, "###################################################");
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#1 $finish;
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end
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event reset_done;
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initial
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forever begin
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@ (reset_enable);
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@ (negedge clk)
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$fdisplay (file, "Applying reset");
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reset = 1;
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@ (negedge clk)
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reset = 0;
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$fdisplay (file, "Came out of Reset");
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-> reset_done;
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end
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initial begin
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#10 -> reset_enable;
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@ (reset_done);
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@ (negedge clk);
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enable = 1;
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repeat (5)
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begin
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@ (negedge clk);
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end
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enable = 0;
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#5 -> terminate_sim;
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end
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reg [3:0] count_compare;
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always @ (posedge clk)
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if (reset == 1'b1)
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count_compare <= 0;
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else if ( enable == 1'b1)
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count_compare <= count_compare + 1;
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always @ (negedge clk)
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if (count_compare != count) begin
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$fdisplay (file, "DUT ERROR AT TIME%d",$time);
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$fdisplay (file, "Expected value %d, Got Value %d", count_compare, count);
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dut_error = 1;
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#5 -> terminate_sim;
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end
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endmodule
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