mirror of https://github.com/YosysHQ/yosys.git
d3c67ad9b6
added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc |
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blif | ||
btor | ||
edif | ||
ilang | ||
intersynth | ||
spice | ||
verilog |