mirror of https://github.com/YosysHQ/yosys.git
244 lines
7.0 KiB
C++
244 lines
7.0 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "passes/techmap/simplemap.h"
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static SigBit get_bit_or_zero(const SigSpec &sig)
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{
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if (GetSize(sig) == 0)
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return State::S0;
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return sig[0];
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}
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static void run_ice40_opts(Module *module)
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{
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pool<SigBit> optimized_co;
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vector<Cell*> sb_lut_cells;
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SigMap sigmap(module);
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\SB_LUT4")
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{
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sb_lut_cells.push_back(cell);
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continue;
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}
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if (cell->type == "\\SB_CARRY")
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{
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SigSpec non_const_inputs, replacement_output;
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int count_zeros = 0, count_ones = 0;
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SigBit inbit[3] = {
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get_bit_or_zero(cell->getPort("\\I0")),
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get_bit_or_zero(cell->getPort("\\I1")),
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get_bit_or_zero(cell->getPort("\\CI"))
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};
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for (int i = 0; i < 3; i++)
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if (inbit[i].wire == nullptr) {
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if (inbit[i] == State::S1)
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count_ones++;
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else
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count_zeros++;
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} else
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non_const_inputs.append(inbit[i]);
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if (count_zeros >= 2)
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replacement_output = State::S0;
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else if (count_ones >= 2)
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replacement_output = State::S1;
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else if (GetSize(non_const_inputs) == 1)
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replacement_output = non_const_inputs;
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if (GetSize(replacement_output)) {
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optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
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module->connect(cell->getPort("\\CO")[0], replacement_output);
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module->design->scratchpad_set_bool("opt.did_something", true);
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log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
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log_id(module), log_id(cell), log_signal(replacement_output));
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module->remove(cell);
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}
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continue;
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}
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if (cell->type == "$__ICE40_FULL_ADDER")
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{
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SigSpec non_const_inputs, replacement_output;
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int count_zeros = 0, count_ones = 0;
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SigBit inbit[3] = {
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cell->getPort("\\A"),
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cell->getPort("\\B"),
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cell->getPort("\\CI")
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};
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for (int i = 0; i < 3; i++)
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if (inbit[i].wire == nullptr) {
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if (inbit[i] == State::S1)
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count_ones++;
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else
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count_zeros++;
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} else
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non_const_inputs.append(inbit[i]);
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if (count_zeros >= 2)
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replacement_output = State::S0;
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else if (count_ones >= 2)
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replacement_output = State::S1;
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else if (GetSize(non_const_inputs) == 1)
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replacement_output = non_const_inputs;
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if (GetSize(replacement_output)) {
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optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
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module->connect(cell->getPort("\\CO")[0], replacement_output);
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module->design->scratchpad_set_bool("opt.did_something", true);
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log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
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log_id(module), log_id(cell), log_signal(replacement_output));
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cell->type = "$lut";
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cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
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cell->setPort("\\Y", cell->getPort("\\O"));
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cell->unsetPort("\\B");
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cell->unsetPort("\\CI");
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cell->unsetPort("\\CO");
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cell->unsetPort("\\O");
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cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
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cell->setParam("\\WIDTH", 4);
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}
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continue;
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}
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}
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for (auto cell : sb_lut_cells)
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{
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SigSpec inbits;
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inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
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sigmap.apply(inbits);
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if (optimized_co.count(inbits[0])) goto remap_lut;
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if (optimized_co.count(inbits[1])) goto remap_lut;
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if (optimized_co.count(inbits[2])) goto remap_lut;
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if (optimized_co.count(inbits[3])) goto remap_lut;
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if (!sigmap(inbits).is_fully_const())
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continue;
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remap_lut:
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module->design->scratchpad_set_bool("opt.did_something", true);
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log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
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cell->type ="$lut";
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cell->setParam("\\WIDTH", 4);
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cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
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cell->unsetParam("\\LUT_INIT");
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cell->setPort("\\A", SigSpec({
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get_bit_or_zero(cell->getPort("\\I3")),
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get_bit_or_zero(cell->getPort("\\I2")),
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get_bit_or_zero(cell->getPort("\\I1")),
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get_bit_or_zero(cell->getPort("\\I0"))
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}));
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cell->setPort("\\Y", cell->getPort("\\O")[0]);
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cell->unsetPort("\\I0");
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cell->unsetPort("\\I1");
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cell->unsetPort("\\I2");
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cell->unsetPort("\\I3");
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cell->unsetPort("\\O");
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cell->check();
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simplemap_lut(module, cell);
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module->remove(cell);
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}
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}
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struct Ice40OptPass : public Pass {
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Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_opt [options] [selection]\n");
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log("\n");
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log("This command executes the following script:\n");
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log("\n");
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log(" do\n");
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log(" <ice40 specific optimizations>\n");
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log(" opt_expr -mux_undef -undriven [-full]\n");
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log(" opt_merge\n");
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log(" opt_rmdff\n");
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log(" opt_clean\n");
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log(" while <changed design>\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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string opt_expr_args = "-mux_undef -undriven";
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log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
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log_push();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-full") {
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opt_expr_args += " -full";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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while (1)
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{
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design->scratchpad_unset("opt.did_something");
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log_header(design, "Running ICE40 specific optimizations.\n");
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for (auto module : design->selected_modules())
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run_ice40_opts(module);
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Pass::call(design, "opt_expr " + opt_expr_args);
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Pass::call(design, "opt_merge");
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Pass::call(design, "opt_rmdff");
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Pass::call(design, "opt_clean");
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if (design->scratchpad_get_bool("opt.did_something") == false)
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break;
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log_header(design, "Rerunning OPT passes. (Removed registers in this run.)\n");
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}
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design->optimize();
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design->sort();
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design->check();
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log_header(design, "Finished OPT passes. (There is nothing left to do.)\n");
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log_pop();
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}
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} Ice40OptPass;
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PRIVATE_NAMESPACE_END
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