riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/docs/resources/PRESENTATION_Prog/absval_ref.v

4 lines
97 B
Verilog
Raw Blame History

module absval_ref(input signed [3:0] a, output [3:0] y);
assign y = a[3] ? -a : a;
endmodule
Reference in New Issue View Git Blame Copy Permalink