mirror of https://github.com/YosysHQ/yosys.git
458 lines
15 KiB
ReStructuredText
458 lines
15 KiB
ReStructuredText
Typical phases of a synthesis flow
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----------------------------------
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.. role:: yoscrypt(code)
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:language: yoscrypt
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.. todo:: should e.g. :yoscrypt:`proc` and :yoscrypt:`memory` examples be
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included here (typical phases) or examples
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.. todo:: expand bullet points
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- Reading and elaborating the design
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- Higher-level synthesis and optimization
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- Converting ``always``-blocks to logic and registers
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- Perform coarse-grain optimizations (resource sharing, const folding, ...)
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- Handling of memories and other coarse-grain blocks
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- Extracting and optimizing finite state machines
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- Convert remaining logic to bit-level logic functions
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- Perform optimizations on bit-level logic functions
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- Map bit-level logic gates and registers to cell library
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- Write results to output file
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Reading the design
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~~~~~~~~~~~~~~~~~~
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.. todo:: include ``read_verilog <<EOF`` when discussing how to read designs?
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.. code-block:: yoscrypt
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read_verilog file1.v
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read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
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read_verilog -lib cell_library.v
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verilog_defaults -add -I include_dir
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read_verilog file3.v
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read_verilog file4.v
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verilog_defaults -clear
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verilog_defaults -push
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verilog_defaults -add -I include_dir
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read_verilog file5.v
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read_verilog file6.v
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verilog_defaults -pop
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Design elaboration
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~~~~~~~~~~~~~~~~~~
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During design elaboration Yosys figures out how the modules are hierarchically
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connected. It also re-runs the AST parts of the Verilog frontend to create all
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needed variations of parametric modules.
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.. todo:: hierarchy without ``-top`` is bad
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- resolve non-module-specific references (sub modules, interfaces et al)
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- check sub modules exist, discarding unused
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- set top attribute
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- also mention failure modes
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- also prep?
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.. code-block:: yoscrypt
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# simplest form. at least this version should be used after reading all input files
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#
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hierarchy
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# recommended form. fails if parts of the design hierarchy are missing, removes
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# everything that is unreachable from the top module, and marks the top module.
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#
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hierarchy -check -top top_module
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Converting process blocks
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~~~~~~~~~~~~~~~~~~~~~~~~~
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The Verilog frontend converts ``always``-blocks to RTL netlists for the
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expressions and "processess" for the control- and memory elements. The
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:cmd:ref:`proc` command then transforms these "processess" to netlists of RTL
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multiplexer and register cells. It also is a macro command that calls the other
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``proc_*`` commands in a sensible order:
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#. :cmd:ref:`proc_clean` removes empty branches and processes.
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#. :cmd:ref:`proc_rmdead` removes unreachable branches.
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#. :cmd:ref:`proc_prune`
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#. :cmd:ref:`proc_init` special handling of "initial" blocks.
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#. :cmd:ref:`proc_arst` identifies modeling of async resets.
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#. :cmd:ref:`proc_rom`
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#. :cmd:ref:`proc_mux` converts decision trees to multiplexer networks.
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#. :cmd:ref:`proc_dlatch`
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#. :cmd:ref:`proc_dff` extracts registers from processes.
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#. :cmd:ref:`proc_memwr`
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#. :cmd:ref:`proc_clean` this should remove all the processes, provided all went
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fine.
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After all the ``proc_*`` commands, :yoscrypt:`opt_expr` is called. This can be
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disabled by calling :yoscrypt:`proc -noopt`. For more information about
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:cmd:ref:`proc`, such as disabling certain sub commands, see :doc:`/cmd/proc`.
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Many commands can not operate on modules with "processess" in them. Usually a
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call to :cmd:ref:`proc` is the first command in the actual synthesis procedure
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after design elaboration.
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Example
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^^^^^^^
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.. todo:: describe ``proc`` images
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.. literalinclude:: /code_examples/synth_flow/proc_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/proc_01.v``
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.. literalinclude:: /code_examples/synth_flow/proc_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/proc_01.ys``
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.. figure:: /_images/code_examples/synth_flow/proc_01.*
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:class: width-helper
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.. figure:: /_images/code_examples/synth_flow/proc_02.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/proc_02.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/proc_02.v``
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.. literalinclude:: /code_examples/synth_flow/proc_02.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/proc_02.ys``
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.. figure:: /_images/code_examples/synth_flow/proc_03.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/proc_03.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/proc_03.ys``
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.. literalinclude:: /code_examples/synth_flow/proc_03.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/proc_03.v``
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Optimizations
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~~~~~~~~~~~~~
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The :cmd:ref:`opt` command implements a series of simple optimizations. It also
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is a macro command that calls other commands:
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.. code-block:: yoscrypt
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opt_expr # const folding and simple expression rewriting
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opt_merge -nomux # merging identical cells
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do
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opt_muxtree # remove never-active branches from multiplexer tree
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opt_reduce # consolidate trees of boolean ops to reduce functions
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opt_merge # merging identical cells
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opt_rmdff # remove/simplify registers with constant inputs
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opt_clean # remove unused objects (cells, wires) from design
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opt_expr # const folding and simple expression rewriting
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while [changed design]
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The command :cmd:ref:`clean` can be used as alias for :cmd:ref:`opt_clean`. And
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``;;`` can be used as shortcut for :cmd:ref:`clean`. For example:
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.. code-block:: yoscrypt
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hierarchy; proc; opt; memory; opt_expr;; fsm;;
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Example
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"""""""
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.. todo:: describe ``opt`` images
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.. figure:: /_images/code_examples/synth_flow/opt_01.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/opt_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/opt_01.ys``
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.. literalinclude:: /code_examples/synth_flow/opt_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/opt_01.v``
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.. figure:: /_images/code_examples/synth_flow/opt_02.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/opt_02.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/opt_02.ys``
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.. literalinclude:: /code_examples/synth_flow/opt_02.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/opt_02.v``
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.. figure:: /_images/code_examples/synth_flow/opt_03.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/opt_03.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/opt_03.ys``
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.. literalinclude:: /code_examples/synth_flow/opt_03.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/opt_03.v``
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.. figure:: /_images/code_examples/synth_flow/opt_04.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/opt_04.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/opt_04.v``
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.. literalinclude:: /code_examples/synth_flow/opt_04.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/opt_04.ys``
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When to use :cmd:ref:`opt` or :cmd:ref:`clean`
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""""""""""""""""""""""""""""""""""""""""""""""
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Usually it does not hurt to call :cmd:ref:`opt` after each regular command in
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the synthesis script. But it increases the synthesis time, so it is favourable
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to only call :cmd:ref:`opt` when an improvement can be achieved.
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It is generally a good idea to call :cmd:ref:`opt` before inherently expensive
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commands such as :cmd:ref:`sat` or :cmd:ref:`freduce`, as the possible gain is
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much higher in these cases as the possible loss.
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The :cmd:ref:`clean` command on the other hand is very fast and many commands
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leave a mess (dangling signal wires, etc). For example, most commands do not
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remove any wires or cells. They just change the connections and depend on a
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later call to clean to get rid of the now unused objects. So the occasional
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``;;`` is a good idea in every synthesis script.
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Other common optimization commands
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. todo:: fill out descriptions for other optimization commands
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:cmd:ref:`wreduce`
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Reduces the word size of operations.
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:cmd:ref:`peepopt`
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Applies a collection of peephole optimizers to the current design.
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:cmd:ref:`share`
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Merges shareable resources into a single resource using a SAT solver to
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determine if two resources are shareable.
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Memory handling
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~~~~~~~~~~~~~~~
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In the RTL netlist, memory reads and writes are individual cells. This makes
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consolidating the number of ports for a memory easier. The :cmd:ref:`memory`
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transforms memories to an implementation. Per default that is logic for address
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decoders and registers. It also is a macro command that calls the other
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``memory_*`` commands in a sensible order:
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.. todo:: fill out missing :cmd:ref:`memory` subcommands descriptions
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#. :cmd:ref:`memory_bmux2rom`
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#. :cmd:ref:`memory_dff` merges registers into the memory read- and write cells.
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#. :cmd:ref:`memory_share`
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#. :cmd:ref:`memory_memx`
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#. :cmd:ref:`memory_collect` collects all read and write cells for a memory and
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transforms them into one multi-port memory cell.
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#. :cmd:ref:`memory_bram`
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#. :cmd:ref:`memory_map` takes the multi-port memory cell and transforms it to
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address decoder logic and registers.
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.. todo:: is :yoscrypt:`memory -nomap; techmap -map my_memory_map.v; memory_map`
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superceded by :yoscrypt:`memory_libmap`?
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Usually it is preferred to use architecture-specific RAM resources for memory.
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For example:
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.. code-block:: yoscrypt
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memory -nomap; techmap -map my_memory_map.v; memory_map
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For more information about :cmd:ref:`memory`, such as disabling certain sub
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commands, see :doc:`/cmd/memory`.
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Example
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^^^^^^^
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.. todo:: describe ``memory`` images
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.. figure:: /_images/code_examples/synth_flow/memory_01.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/memory_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/memory_01.ys``
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.. literalinclude:: /code_examples/synth_flow/memory_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/memory_01.v``
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.. figure:: /_images/code_examples/synth_flow/memory_02.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/memory_02.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/memory_02.v``
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.. literalinclude:: /code_examples/synth_flow/memory_02.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/memory_02.ys``
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The :cmd:ref:`memory_libmap` command
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. todo:: :cmd:ref:`memory_libmap` description
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FSM handling
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~~~~~~~~~~~~
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The :cmd:ref:`fsm` command identifies, extracts, optimizes (re-encodes), and
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re-synthesizes finite state machines. It again is a macro that calls a series of
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other commands:
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#. :cmd:ref:`fsm_detect` identifies FSM state registers and marks them
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with the ``(* fsm_encoding = "auto" *)`` attribute, if they do not have the
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``fsm_encoding`` set already. Mark registers with ``(* fsm_encoding = "none"
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*)`` to disable FSM optimization for a register.
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#. :cmd:ref:`fsm_extract` replaces the entire FSM (logic and state registers)
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with a ``$fsm`` cell.
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#. :cmd:ref:`fsm_opt` optimizes the FSM. Called multiple times.
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#. :cmd:ref:`fsm_expand` optionally merges additional auxilliary gates into the
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``$fsm`` cell.
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#. :cmd:ref:`fsm_recode` also optimizes the FSM.
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#. :cmd:ref:`fsm_info` logs internal FSM information.
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#. :cmd:ref:`fsm_export` optionally exports each FSM to KISS2 files.
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#. :cmd:ref:`fsm_map` converts the (optimized) ``$fsm`` cell back to logic and
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registers.
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See also :doc:`/cmd/fsm`.
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DSP handling
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~~~~~~~~~~~~
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.. todo:: add info about dsp handling
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Technology mapping
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~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`techmap` command replaces cells with implementations given as
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verilog source. For example implementing a 32 bit adder using 16 bit adders:
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.. figure:: /_images/code_examples/synth_flow/techmap_01.*
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:class: width-helper
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.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/techmap_01_map.v``
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.. literalinclude:: /code_examples/synth_flow/techmap_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/techmap_01.v``
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.. literalinclude:: /code_examples/synth_flow/techmap_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/techmap_01.ys``
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See :doc:`/yosys_internals/techmap` for more.
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stdcell mapping
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^^^^^^^^^^^^^^^
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When :cmd:ref:`techmap` is used without a map file, it uses a built-in map file
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to map all RTL cell types to a generic library of built-in logic gates and
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registers.
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The built-in logic gate types are: ``$_NOT_``, ``$_AND_``, ``$_OR_``,
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``$_XOR_``, and ``$_MUX_``.
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The register types are: ``$_SR_NN_``, ``$_SR_NP_``, ``$_SR_PN_``, ``$_SR_PP_``,
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``$_DFF_N_``, ``$_DFF_P_ $_DFF_NN0_``, ``$_DFF_NN1_``, ``$_DFF_NP0_``,
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``$_DFF_NP1_``, ``$_DFF_PN0_``, ``$_DFF_PN1_``, ``$_DFF_PP0_ $_DFF_PP1_``,
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``$_DFFSR_NNN_``, ``$_DFFSR_NNP_``, ``$_DFFSR_NPN_``, ``$_DFFSR_NPP_``,
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``$_DFFSR_PNN_ $_DFFSR_PNP_``, ``$_DFFSR_PPN_``, ``$_DFFSR_PPP_``,
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``$_DLATCH_N_``, and ``$_DLATCH_P_``.
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See :doc:`/yosys_internals/formats/cell_library` for more about the internal
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cells used.
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The :cmd:ref:`abc` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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The :cmd:ref:`abc` command provides an interface to ABC_, an open source tool
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for low-level logic synthesis.
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.. _ABC: http://www.eecs.berkeley.edu/~alanmi/abc/
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The :cmd:ref:`abc` command processes a netlist of internal gate types and can
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perform:
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- logic minimization (optimization)
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- mapping of logic to standard cell library (liberty format)
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- mapping of logic to k-LUTs (for FPGA synthesis)
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Optionally :cmd:ref:`abc` can process registers from one clock domain and
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perform sequential optimization (such as register balancing).
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ABC is also controlled using scripts. An ABC script can be specified to use more
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advanced ABC features. It is also possible to write the design with
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:cmd:ref:`write_blif` and load the output file into ABC outside of Yosys.
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Example
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^^^^^^^
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.. todo:: describe ``abc`` images
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.. literalinclude:: /code_examples/synth_flow/abc_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/abc_01.v``
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.. literalinclude:: /code_examples/synth_flow/abc_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/abc_01.ys``
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.. figure:: /_images/code_examples/synth_flow/abc_01.*
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:class: width-helper
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Other special-purpose mapping commands
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The commands below may be used depending on the targeted architecture for
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compatibility with, or to take advantage of, resources available.
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:cmd:ref:`dfflibmap`
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This command maps the internal register cell types to the register types
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described in a liberty file.
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:cmd:ref:`hilomap`
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Some architectures require special driver cells for driving a constant hi or
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lo value. This command replaces simple constants with instances of such
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driver cells.
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:cmd:ref:`iopadmap`
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Top-level input/outputs must usually be implemented using special I/O-pad
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cells. This command inserts such cells to the design.
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:cmd:ref:`alumacc`
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Translate arithmetic operations like $add, $mul, $lt, etc. to $alu and $macc
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cells.
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:cmd:ref:`dfflegalize`
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Specify a set of supported FF cells/cell groups and convert all FFs to them.
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:cmd:ref:`deminout`
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Convert inout ports to input or output ports, if possible.
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:cmd:ref:`pmuxtree`
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Transforms parallel mux cells, ``$pmux``, to trees of ``$mux`` cells.
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