mirror of https://github.com/YosysHQ/yosys.git
22 lines
365 B
Plaintext
22 lines
365 B
Plaintext
# read design
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read_verilog counter.v
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hierarchy -check -top counter
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# the high-level stuff
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proc; opt; memory; opt; fsm; opt
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# mapping to internal cell library
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techmap; opt
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# mapping flip-flops to mycells.lib
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dfflibmap -liberty mycells.lib
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# mapping logic to mycells.lib
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abc -liberty mycells.lib
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# cleanup
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clean
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# write synthesized design
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write_verilog synth.v
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