mirror of https://github.com/YosysHQ/yosys.git
Preserve 'signed'-ness of a verilog wire through RTLIL |
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.. | ||
Makefile.inc | ||
ast.cc | ||
ast.h | ||
dpicall.cc | ||
genrtlil.cc | ||
simplify.cc |
Preserve 'signed'-ness of a verilog wire through RTLIL |
||
---|---|---|
.. | ||
Makefile.inc | ||
ast.cc | ||
ast.h | ||
dpicall.cc | ||
genrtlil.cc | ||
simplify.cc |