yosys/frontends/ast
whitequark 3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
..
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
ast.cc Add AST_SELFSZ and improve handling of bit slices 2020-05-02 11:21:01 +02:00
ast.h Add AST_SELFSZ and improve handling of bit slices 2020-05-02 11:21:01 +02:00
dpicall.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
genrtlil.cc Merge pull request #2006 from jersey99/signed-in-rtlil-wire 2020-06-04 11:23:06 +00:00
simplify.cc Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 2020-05-29 16:52:11 +02:00