mirror of https://github.com/YosysHQ/yosys.git
253 lines
7.4 KiB
C++
253 lines
7.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "opt_status.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include "libs/sha1/sha1.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <set>
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struct OptReduceWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap assign_map;
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int total_count;
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bool did_something;
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void opt_reduce(std::set<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*> &drivers, RTLIL::Cell *cell)
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{
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if (cells.count(cell) == 0)
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return;
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cells.erase(cell);
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RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
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sig_a.sort_and_unify();
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sig_a.expand();
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RTLIL::SigSpec new_sig_a;
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for (auto &chunk : sig_a.chunks)
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{
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if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) {
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if (cell->type == "$reduce_and") {
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new_sig_a = RTLIL::SigSpec(RTLIL::State::S0);
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break;
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}
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continue;
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}
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if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S1) {
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if (cell->type == "$reduce_or") {
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new_sig_a = RTLIL::SigSpec(RTLIL::State::S1);
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break;
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}
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continue;
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}
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if (chunk.wire == NULL) {
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new_sig_a.append(chunk);
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continue;
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}
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bool imported_children = false;
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for (auto child_cell : drivers.find(chunk)) {
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if (child_cell->type == cell->type) {
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opt_reduce(cells, drivers, child_cell);
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new_sig_a.append(child_cell->connections["\\A"]);
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imported_children = true;
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}
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}
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if (!imported_children)
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new_sig_a.append(chunk);
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}
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new_sig_a.sort_and_unify();
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if (new_sig_a != sig_a || sig_a.width != cell->connections["\\A"].width) {
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log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
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did_something = true;
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OPT_DID_SOMETHING = true;
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total_count++;
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}
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cell->connections["\\A"] = new_sig_a;
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.width);
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return;
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}
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void opt_mux(RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
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RTLIL::SigSpec sig_b = assign_map(cell->connections["\\B"]);
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RTLIL::SigSpec sig_s = assign_map(cell->connections["\\S"]);
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RTLIL::SigSpec new_sig_b, new_sig_s;
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std::set<RTLIL::SigSpec> handled_sig;
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handled_sig.insert(sig_a);
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for (int i = 0; i < sig_s.width; i++)
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{
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RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.width, sig_a.width);
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if (handled_sig.count(this_b) > 0)
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continue;
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RTLIL::SigSpec this_s = sig_s.extract(i, 1);
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for (int j = i+1; j < sig_s.width; j++) {
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RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.width, sig_a.width);
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if (this_b == that_b)
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this_s.append(sig_s.extract(j, 1));
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}
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if (this_s.width > 1)
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{
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RTLIL::Wire *reduce_or_wire = new RTLIL::Wire;
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reduce_or_wire->name = NEW_ID;
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module->wires[reduce_or_wire->name] = reduce_or_wire;
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RTLIL::Cell *reduce_or_cell = new RTLIL::Cell;
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reduce_or_cell->name = NEW_ID;
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reduce_or_cell->type = "$reduce_or";
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reduce_or_cell->connections["\\A"] = this_s;
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reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.width);
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reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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module->cells[reduce_or_cell->name] = reduce_or_cell;
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this_s = RTLIL::SigSpec(reduce_or_wire);
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reduce_or_cell->connections["\\Y"] = this_s;
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}
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new_sig_b.append(this_b);
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new_sig_s.append(this_s);
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handled_sig.insert(this_b);
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}
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if (new_sig_s.width != sig_s.width) {
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log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
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did_something = true;
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OPT_DID_SOMETHING = true;
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total_count++;
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}
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if (new_sig_s.width == 0)
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{
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module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"]));
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assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]);
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module->cells.erase(cell->name);
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delete cell;
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}
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else
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{
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cell->connections["\\B"] = new_sig_b;
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cell->connections["\\S"] = new_sig_s;
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if (new_sig_s.width > 1) {
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cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.width);
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} else {
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cell->type = "$mux";
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cell->parameters.erase("\\S_WIDTH");
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}
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}
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}
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OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module) :
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design(design), module(module), assign_map(module)
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{
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log(" Optimizing cells in module %s.\n", module->name.c_str());
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total_count = 0;
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did_something = true;
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while (did_something)
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{
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did_something = false;
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// merge trees of reduce_* cells to one single cell and unify input vectors
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// (only handle recduce_and and reduce_or for various reasons)
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const char *type_list[] = { "$reduce_or", "$reduce_and" };
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for (auto type : type_list)
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{
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SigSet<RTLIL::Cell*> drivers;
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std::set<RTLIL::Cell*> cells;
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for (auto &cell_it : module->cells) {
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type != type || !design->selected(module, cell))
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continue;
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drivers.insert(assign_map(cell->connections["\\Y"]), cell);
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cells.insert(cell);
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}
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while (cells.size() > 0) {
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RTLIL::Cell *cell = *cells.begin();
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opt_reduce(cells, drivers, cell);
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}
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}
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// merge identical inputs on $mux and $pmux cells
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for (auto &cell_it : module->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || !design->selected(module, cell))
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continue;
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opt_mux(cell);
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}
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}
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}
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};
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struct OptReducePass : public Pass {
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OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_reduce [selection]\n");
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log("\n");
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log("This pass performs two interlinked optimizations:\n");
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log("\n");
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log("1. it consolidates trees of large AND gates or OR gates and eliminates\n");
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log("duplicated inputs.\n");
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log("\n");
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log("2. it identifies duplicated inputs to MUXes and replaces them with a single\n");
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log("input with the original control signals OR'ed together.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");
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extra_args(args, 1, design);
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int total_count = 0;
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for (auto &mod_it : design->modules) {
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if (!design->selected(mod_it.second))
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continue;
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OptReduceWorker worker(design, mod_it.second);
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total_count += worker.total_count;
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}
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log("Performed a total of %d changes.\n", total_count);
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}
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} OptReducePass;
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