Vamsi K Vytla 5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL ... As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser		2020-04-27 09:44:24 -07:00
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Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
ilang_backend.cc	Preserve 'signed'-ness of a verilog wire through RTLIL	2020-04-27 09:44:24 -07:00
ilang_backend.h	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00