yosys/docs/source/code_examples/macc/macc_xilinx_xmap.v

11 lines
130 B
Verilog

module DSP48_MACC (a, b, c, y);
input [17:0] a;
input [24:0] b;
input [47:0] c;
output [47:0] y;
assign y = a*b + c;
endmodule