mirror of https://github.com/YosysHQ/yosys.git
69 lines
1.3 KiB
Verilog
69 lines
1.3 KiB
Verilog
module GP_DFFS(input D, CLK, nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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GP_DFFSR #(
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.INIT(INIT),
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.SRMODE(1'b1),
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) _TECHMAP_REPLACE_ (
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.D(D),
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.CLK(CLK),
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.nSR(nSET),
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.Q(Q)
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);
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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GP_DFFSR #(
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.INIT(INIT),
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.SRMODE(1'b0),
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) _TECHMAP_REPLACE_ (
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.D(D),
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.CLK(CLK),
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.nSR(nRST),
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.Q(Q)
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);
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endmodule
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module GP_OBUFT(input IN, input OE, output OUT);
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GP_IOBUF _TECHMAP_REPLACE_ (
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.IN(IN),
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.OE(OE),
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.IO(OUT),
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.OUT()
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);
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endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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if(LUT == 2'b01) begin
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GP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );
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end
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else begin
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GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(1'b0));
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end
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end else
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if (WIDTH == 2) begin
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GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]));
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end else
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if (WIDTH == 3) begin
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GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
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end else
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if (WIDTH == 4) begin
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GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
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.IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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