mirror of https://github.com/YosysHQ/yosys.git
137 lines
3.2 KiB
C++
137 lines
3.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef BITPATTERN_H
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#define BITPATTERN_H
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#include "kernel/log.h"
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#include "kernel/rtlil.h"
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struct BitPatternPool
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{
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int width;
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typedef std::vector<RTLIL::State> bits_t;
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std::set<bits_t> pool;
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BitPatternPool(RTLIL::SigSpec sig)
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{
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width = sig.size();
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if (width > 0) {
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std::vector<RTLIL::State> pattern(width);
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for (int i = 0; i < width; i++) {
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if (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)
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pattern[i] = sig[i].data;
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else
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pattern[i] = RTLIL::State::Sa;
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}
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pool.insert(pattern);
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}
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}
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BitPatternPool(int width)
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{
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this->width = width;
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if (width > 0) {
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std::vector<RTLIL::State> pattern(width);
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for (int i = 0; i < width; i++)
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pattern[i] = RTLIL::State::Sa;
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pool.insert(pattern);
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}
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}
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bits_t sig2bits(RTLIL::SigSpec sig)
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{
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bits_t bits = sig.as_const().bits;
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for (auto &b : bits)
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if (b > RTLIL::State::S1)
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b = RTLIL::State::Sa;
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return bits;
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}
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bool match(bits_t a, bits_t b)
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{
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log_assert(int(a.size()) == width);
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log_assert(int(b.size()) == width);
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for (int i = 0; i < width; i++)
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if (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])
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return false;
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return true;
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}
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bool has_any(RTLIL::SigSpec sig)
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{
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bits_t bits = sig2bits(sig);
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for (auto &it : pool)
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if (match(it, bits))
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return true;
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return false;
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}
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bool has_all(RTLIL::SigSpec sig)
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{
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bits_t bits = sig2bits(sig);
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for (auto &it : pool)
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if (match(it, bits)) {
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for (int i = 0; i < width; i++)
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if (bits[i] > RTLIL::State::S1 && it[i] <= RTLIL::State::S1)
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goto next_pool_entry;
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return true;
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next_pool_entry:;
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}
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return false;
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}
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bool take(RTLIL::SigSpec sig)
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{
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bool status = false;
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bits_t bits = sig2bits(sig);
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std::vector<bits_t> pattern_list;
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for (auto &it : pool)
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if (match(it, bits))
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pattern_list.push_back(it);
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for (auto pattern : pattern_list) {
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pool.erase(pattern);
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for (int i = 0; i < width; i++) {
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if (pattern[i] != RTLIL::State::Sa || bits[i] == RTLIL::State::Sa)
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continue;
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bits_t new_pattern = pattern;
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new_pattern[i] = bits[i] == RTLIL::State::S1 ? RTLIL::State::S0 : RTLIL::State::S1;
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pool.insert(new_pattern);
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}
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status = true;
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}
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return status;
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}
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bool take_all()
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{
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if (pool.empty())
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return false;
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pool.clear();
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return true;
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}
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bool empty()
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{
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return pool.empty();
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}
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};
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#endif
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