mirror of https://github.com/YosysHQ/yosys.git
197 lines
3.9 KiB
Verilog
197 lines
3.9 KiB
Verilog
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module memtest00(clk, setA, setB, y);
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input clk, setA, setB;
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output y;
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reg mem [1:0];
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always @(posedge clk) begin
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if (setA) mem[0] <= 0; // this is line 9
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if (setB) mem[0] <= 1; // this is line 10
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end
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assign y = mem[0];
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endmodule
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// ----------------------------------------------------------
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module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
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input clk, wr_en;
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input [3:0] wr_addr, rd_addr;
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input [7:0] wr_value;
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output reg [7:0] rd_value;
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reg [7:0] data [15:0];
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always @(posedge clk)
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if (wr_en)
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data[wr_addr] <= wr_value;
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always @(posedge clk)
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rd_value <= data[rd_addr];
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endmodule
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// ----------------------------------------------------------
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module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
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input clk, setA, setB;
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input [1:0] addr;
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input [2:0] bit;
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output reg y1, y2;
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output y3, y4;
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reg [7:0] mem1 [3:0];
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(* mem2reg *)
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reg [7:0] mem2 [3:0];
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always @(posedge clk) begin
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if (setA) begin
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mem1[0] <= 10;
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mem1[1] <= 20;
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mem1[2] <= 30;
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mem2[0] <= 17;
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mem2[1] <= 27;
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mem2[2] <= 37;
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end
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if (setB) begin
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mem1[0] <= 1;
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mem1[1] <= 2;
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mem1[2] <= 3;
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mem2[0] <= 71;
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mem2[1] <= 72;
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mem2[2] <= 73;
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end
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y1 <= mem1[addr][bit];
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y2 <= mem2[addr][bit];
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end
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assign y3 = mem1[addr][bit];
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assign y4 = mem2[addr][bit];
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endmodule
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// ----------------------------------------------------------
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module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
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input clk, wr_enable;
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input [3:0] wr_addr, wr_data, rd_addr;
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output reg [3:0] rd_data;
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reg [3:0] memory [0:15];
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always @(posedge clk) begin
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if (wr_enable)
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memory[wr_addr] <= wr_data;
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rd_data <= memory[rd_addr];
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end
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endmodule
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// ----------------------------------------------------------
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module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
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input clk, wr_enable;
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input [3:0] wr_addr, wr_data, rd_addr;
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output [3:0] rd_data;
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reg rd_addr_buf;
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reg [3:0] memory [0:15];
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always @(posedge clk) begin
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if (wr_enable)
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memory[wr_addr] <= wr_data;
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rd_addr_buf <= rd_addr;
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end
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assign rd_data = memory[rd_addr_buf];
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endmodule
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// ----------------------------------------------------------
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module memtest05(clk, addr, wdata, rdata, wen);
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input clk;
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input [1:0] addr;
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input [7:0] wdata;
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output reg [7:0] rdata;
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input [3:0] wen;
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reg [7:0] mem [0:3];
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integer i;
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always @(posedge clk) begin
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for (i = 0; i < 4; i = i+1)
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if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
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rdata <= mem[addr];
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end
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endmodule
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// ----------------------------------------------------------
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module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
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(* gentb_constant=0 *) wire rst;
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reg [7:0] test [0:7];
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integer i;
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always @(posedge clk) begin
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if (rst) begin
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for (i=0; i<8; i=i+1)
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test[i] <= 0;
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end else begin
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test[0][2] <= din[1];
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test[0][5] <= test[0][2];
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test[idx][3] <= din[idx];
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test[idx][6] <= test[idx][2];
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test[idx][idx] <= !test[idx][idx];
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end
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end
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assign dout = test[idx];
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endmodule
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module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
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(* gentb_constant=0 *) wire rst;
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reg [7:0] test [0:7];
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integer i;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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for (i=0; i<8; i=i+1)
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test[i] <= 0;
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end else begin
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test[0][2] <= din[1];
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test[0][5] <= test[0][2];
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test[idx][3] <= din[idx];
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test[idx][6] <= test[idx][2];
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test[idx][idx] <= !test[idx][idx];
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end
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end
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assign dout = test[idx];
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endmodule
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// ----------------------------------------------------------
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module memtest07(clk, addr, woffset, wdata, rdata);
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input clk;
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input [1:0] addr;
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input [3:0] wdata;
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input [1:0] woffset;
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output reg [7:0] rdata;
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reg [7:0] mem [0:3];
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integer i;
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always @(posedge clk) begin
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mem[addr][woffset +: 4] <= wdata;
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rdata <= mem[addr];
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end
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endmodule
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