mirror of https://github.com/YosysHQ/yosys.git
245 lines
3.8 KiB
Verilog
245 lines
3.8 KiB
Verilog
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module test_def(a, y);
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`define MSB_LSB_SEP :
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`define get_msb(off, len) ((off)+(len)-1)
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`define get_lsb(off, len) (off)
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`define sel_bits(offset, len) `get_msb(offset, len) `MSB_LSB_SEP `get_lsb(offset, len)
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input [31:0] a;
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output [7:0] y;
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assign y = a[`sel_bits(16, 8)];
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endmodule
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// ---------------------------------------------------
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module test_ifdef(a, y);
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input [2:0] a;
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output reg [31:0] y;
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always @* begin
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y = 0;
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`undef X
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`ifdef X
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y = y + 42;
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`else
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`undef A
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`undef B
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`ifdef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`undef A
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`define B
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`ifdef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`undef B
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`ifdef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`define B
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`ifdef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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// ------------------------------------
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`undef A
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`undef B
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`ifndef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`undef A
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`define B
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`ifndef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`undef B
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`ifndef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`define B
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`ifndef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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// ------------------------------------
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`undef A
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`ifdef A
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y = (y << 1) | a[0];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`ifdef A
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y = (y << 1) | a[0];
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`else
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y = (y << 1) | a[2];
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`endif
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// ------------------------------------
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`undef A
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`ifndef A
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y = (y << 1) | a[0];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`ifndef A
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y = (y << 1) | a[0];
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`else
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y = (y << 1) | a[2];
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`endif
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`endif
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`define X
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`ifdef X
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`undef A
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`undef B
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`ifdef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`undef A
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`define B
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`ifdef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`undef B
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`ifdef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`define B
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`ifdef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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// ------------------------------------
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`undef A
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`undef B
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`ifndef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`undef A
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`define B
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`ifndef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`undef B
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`ifndef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`define B
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`ifndef A
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y = (y << 1) | a[0];
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`elsif B
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y = (y << 1) | a[1];
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`else
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y = (y << 1) | a[2];
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`endif
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// ------------------------------------
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`undef A
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`ifdef A
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y = (y << 1) | a[0];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`ifdef A
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y = (y << 1) | a[0];
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`else
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y = (y << 1) | a[2];
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`endif
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// ------------------------------------
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`undef A
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`ifndef A
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y = (y << 1) | a[0];
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`else
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y = (y << 1) | a[2];
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`endif
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`define A
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`ifndef A
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y = (y << 1) | a[0];
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`else
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y = (y << 1) | a[2];
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`endif
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`else
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y = y + 42;
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`endif
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end
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endmodule
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`define SIZE 4 // comment supported in this part
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module test_comment_in_macro ( din_a, dout_a );
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input [`SIZE-1:0] din_a;
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output [`SIZE-1:0] dout_a;
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assign dout_a = din_a | `SIZE'ha;
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endmodule
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