Clifford Wolf 91dd87e60b Improved scope resolution of local regs in Verilog+AST frontend		2014-08-05 12:15:53 +02:00
..
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
ast.cc	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
ast.h	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
genrtlil.cc	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
simplify.cc	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00