mirror of https://github.com/YosysHQ/yosys.git
46 lines
1.8 KiB
Plaintext
46 lines
1.8 KiB
Plaintext
read_verilog ../common/mux.v
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design -save read
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hierarchy -top mux2
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-none t:MISTRAL_ALUT3 %% t:* %D
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design -load read
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hierarchy -top mux4
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux4 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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hierarchy -top mux8
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 1 t:MISTRAL_ALUT5
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select -assert-count 2 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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design -load read
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hierarchy -top mux16
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proc
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equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux16 # Constrain all select calls below inside the top module
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select -assert-count 1 t:MISTRAL_ALUT3
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select -assert-count 2 t:MISTRAL_ALUT5
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select -assert-count 4 t:MISTRAL_ALUT6
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select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
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