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read_verilog <<EOT
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|
module led_blink (
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input clk,
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|
output ledc
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|
);
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|
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reg [6:0] led_counter = 0;
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always @( posedge clk ) begin
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|
led_counter <= led_counter + 1;
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|
end
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assign ledc = !led_counter[ 6:3 ];
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|
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|
endmodule
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|
EOT
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|
proc
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|
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9
|