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yosys/techlibs
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Clifford Wolf 44b5bd4b63 Fixed simlib $macc model for xilinx xsim 2014-09-08 17:09:39 +02:00
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cmos Added test comments to techlibs/cmos/cmos_cells.lib 2014-01-29 10:51:02 +01:00
common Fixed simlib $macc model for xilinx xsim 2014-09-08 17:09:39 +02:00
xilinx Renamed $lut ports to follow A-Y naming scheme 2014-08-15 14:18:40 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00