Zachary Snow b2e9717419 sv: support declaration in generate for initialization ... This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.		2021-08-31 12:34:55 -06:00
..
.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
Makefile.inc	Treat all bison warnings as errors in verilog front-end	2020-07-15 11:57:31 +02:00
const2ast.cc	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
preproc.cc	verilog: save and restore overwritten macro arguments	2021-07-28 21:52:16 -04:00
preproc.h	verilog: save and restore overwritten macro arguments	2021-07-28 21:52:16 -04:00
verilog_frontend.cc	verilog: Squash a memory leak.	2021-06-14 17:07:41 +02:00
verilog_frontend.h	verilog: Squash a memory leak.	2021-06-14 17:07:41 +02:00
verilog_lexer.l	verilog: Support tri/triand/trior wire types.	2021-08-06 21:35:43 +02:00
verilog_parser.y	sv: support declaration in generate for initialization	2021-08-31 12:34:55 -06:00