mirror of https://github.com/YosysHQ/yosys.git
36 lines
562 B
Verilog
36 lines
562 B
Verilog
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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wire [47:0] P_48;
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DSP48A1 #(
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// Disable all registers
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.A0REG(0),
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.A1REG(0),
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.B0REG(0),
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.B1REG(0),
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.CARRYINREG(0),
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.CARRYINSEL("OPMODE5"),
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.CREG(0),
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.DREG(0),
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.MREG(0),
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.OPMODEREG(0),
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.PREG(0)
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) _TECHMAP_REPLACE_ (
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//Data path
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.A(A),
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.B(B),
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.C(48'b0),
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.D(18'b0),
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.P(P_48),
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.OPMODE(8'b0000001)
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);
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assign Y = P_48;
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endmodule
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