yosys/techlibs
Martin Povišer e0fc48e196 quicklogic: Generate `bram_types_sim.v` at build time 2023-12-04 18:21:00 +01:00
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achronix techlibs: fix typo in help message 2023-11-13 16:29:52 +13:00
anlogic anlogic: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
common techlibs: Add `cmp2softlogic.v` to common 2023-11-13 10:42:12 +01:00
coolrunner2 Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00
easic Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ecp5 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
efinix efinix: Use `memory_libmap` pass. 2022-05-18 17:32:56 +02:00
fabulous fabulous: Add support for LUT6s 2023-04-12 18:42:09 +02:00
gatemate gatemate: Prevent implicit declaration of `ram_{we,en}` 2023-06-05 19:08:44 +02:00
gowin gowin: fix typo 2023-11-14 22:37:29 +00:00
greenpak4 Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ice40 ice40: fix -noabc9 2023-11-17 12:49:17 +00:00
intel Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
intel_alm intel_alm: re-enable 8x40-bit M10K support 2023-05-29 06:42:03 +01:00
lattice synth_lattice: Enable `booth` by default on XO3 2023-11-22 15:47:11 +01:00
nexus nexus: Fix format strings to remove space padding 2023-12-03 10:36:34 +01:00
quicklogic quicklogic: Generate `bram_types_sim.v` at build time 2023-12-04 18:21:00 +01:00
sf2 Test fixes for latest iverilog 2022-09-21 15:46:43 +02:00
xilinx Update Xilinx cell definitions, fixes #3699 2023-03-23 09:44:36 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00