mirror of https://github.com/YosysHQ/yosys.git
53 lines
743 B
Verilog
53 lines
743 B
Verilog
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module dff(clk, d, q);
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input clk, d;
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output reg q;
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always @(posedge clk)
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q <= d;
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endmodule
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module dffa(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk or posedge arst) begin
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if (arst)
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q <= 1;
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else
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q <= d;
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end
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endmodule
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module dffa1(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk or negedge arst) begin
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if (~arst)
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q <= 0;
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else
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q <= d;
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end
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endmodule
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module dffa2(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk or negedge arst) begin
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if (!arst)
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q <= 0;
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else
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q <= d;
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end
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endmodule
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module dffa3(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk or negedge arst) begin
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if (~(!arst))
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q <= d;
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else
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q <= 1;
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end
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endmodule
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