mirror of https://github.com/YosysHQ/yosys.git
261 lines
10 KiB
C++
261 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SATGEN_H
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#define SATGEN_H
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#ifdef YOSYS_ENABLE_MINISAT
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# include "libs/ezsat/ezminisat.h"
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typedef ezMiniSAT ezDefaultSAT;
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#else
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# include "libs/ezsat/ezsat.h"
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typedef ezSAT ezDefaultSAT;
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#endif
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struct SatGen
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{
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ezSAT *ez;
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RTLIL::Design *design;
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SigMap *sigmap;
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std::string prefix;
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SigPool initial_state;
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SatGen(ezSAT *ez, RTLIL::Design *design, SigMap *sigmap, std::string prefix = std::string()) :
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ez(ez), design(design), sigmap(sigmap), prefix(prefix)
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{
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}
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void setContext(RTLIL::Design *design, SigMap *sigmap, std::string prefix = std::string())
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{
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this->design = design;
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this->sigmap = sigmap;
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this->prefix = prefix;
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}
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std::vector<int> importSigSpec(RTLIL::SigSpec &sig, int timestep = -1)
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{
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assert(timestep < 0 || timestep > 0);
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RTLIL::SigSpec s = sig;
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sigmap->apply(s);
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s.expand();
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std::vector<int> vec;
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vec.reserve(s.chunks.size());
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for (auto &c : s.chunks)
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if (c.wire == NULL) {
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vec.push_back(c.data.as_bool() ? ez->TRUE : ez->FALSE);
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} else {
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std::string name = prefix;
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name += timestep == -1 ? "" : stringf("@%d:", timestep);
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name += stringf(c.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(c.wire->name), c.offset);
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vec.push_back(ez->literal(name));
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}
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return vec;
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}
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void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell)
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{
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bool is_signed_a = false, is_signed_b = false;
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if (cell->parameters.count("\\A_SIGNED") > 0)
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is_signed_a = cell->parameters["\\A_SIGNED"].as_bool();
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if (cell->parameters.count("\\B_SIGNED") > 0)
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is_signed_b = cell->parameters["\\B_SIGNED"].as_bool();
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while (vec_a.size() < vec_b.size())
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vec_a.push_back(is_signed_a && vec_a.size() > 0 ? vec_a.back() : ez->FALSE);
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while (vec_b.size() < vec_a.size())
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vec_b.push_back(is_signed_b && vec_b.size() > 0 ? vec_b.back() : ez->FALSE);
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}
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void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, std::vector<int> &vec_y, RTLIL::Cell *cell)
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{
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extendSignalWidth(vec_a, vec_b, cell);
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while (vec_y.size() < vec_a.size())
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vec_y.push_back(ez->literal());
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}
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bool importCell(RTLIL::Cell *cell, int timestep = -1)
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{
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if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_" ||
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cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
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cell->type == "$add" || cell->type == "$sub") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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extendSignalWidth(a, b, y, cell);
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if (cell->type == "$and" || cell->type == "$_AND_")
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ez->assume(ez->vec_eq(ez->vec_and(a, b), y));
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if (cell->type == "$or" || cell->type == "$_OR_")
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ez->assume(ez->vec_eq(ez->vec_or(a, b), y));
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if (cell->type == "$xor" || cell->type == "$_XOR_")
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ez->assume(ez->vec_eq(ez->vec_xor(a, b), y));
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if (cell->type == "$xnor")
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ez->assume(ez->vec_eq(ez->vec_not(ez->vec_xor(a, b)), y));
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if (cell->type == "$add")
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ez->assume(ez->vec_eq(ez->vec_add(a, b), y));
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if (cell->type == "$sub")
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ez->assume(ez->vec_eq(ez->vec_sub(a, b), y));
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return true;
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}
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if (cell->type == "$_INV_" || cell->type == "$not") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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ez->assume(ez->vec_eq(ez->vec_not(a), y));
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return true;
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}
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if (cell->type == "$_MUX_" || cell->type == "$mux") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
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std::vector<int> s = importSigSpec(cell->connections.at("\\S"), timestep);
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), y));
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return true;
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}
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if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
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std::vector<int> s = importSigSpec(cell->connections.at("\\S"), timestep);
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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std::vector<int> tmp = a;
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for (size_t i = 0; i < s.size(); i++) {
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std::vector<int> part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size());
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tmp = ez->vec_ite(s.at(i), part_of_b, tmp);
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}
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if (cell->type == "$safe_pmux")
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tmp = ez->vec_ite(ez->onehot(s, true), tmp, a);
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ez->assume(ez->vec_eq(tmp, y));
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return true;
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}
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if (cell->type == "$pos" || cell->type == "$neg") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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if (cell->type == "$pos") {
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ez->assume(ez->vec_eq(a, y));
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} else {
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std::vector<int> zero(a.size(), ez->FALSE);
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ez->assume(ez->vec_eq(ez->vec_sub(zero, a), y));
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}
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return true;
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}
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if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
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cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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if (cell->type == "$reduce_and")
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ez->SET(ez->expression(ez->OpAnd, a), y.at(0));
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if (cell->type == "$reduce_or" || cell->type == "$reduce_bool")
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ez->SET(ez->expression(ez->OpOr, a), y.at(0));
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if (cell->type == "$reduce_xor")
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ez->SET(ez->expression(ez->OpXor, a), y.at(0));
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if (cell->type == "$reduce_xnor")
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ez->SET(ez->NOT(ez->expression(ez->OpXor, a)), y.at(0));
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if (cell->type == "$logic_not")
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ez->SET(ez->NOT(ez->expression(ez->OpOr, a)), y.at(0));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(0, y.at(0));
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return true;
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}
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if (cell->type == "$logic_and" || cell->type == "$logic_or") {
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int a = ez->expression(ez->OpOr, importSigSpec(cell->connections.at("\\A"), timestep));
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int b = ez->expression(ez->OpOr, importSigSpec(cell->connections.at("\\B"), timestep));
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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if (cell->type == "$logic_and")
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ez->SET(ez->expression(ez->OpAnd, a, b), y.at(0));
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else
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ez->SET(ez->expression(ez->OpOr, a, b), y.at(0));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(0, y.at(0));
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return true;
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}
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if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$ge" || cell->type == "$gt") {
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bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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extendSignalWidth(a, b, cell);
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if (cell->type == "$lt")
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ez->SET(is_signed ? ez->vec_lt_signed(a, b) : ez->vec_lt_unsigned(a, b), y.at(0));
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if (cell->type == "$le")
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ez->SET(is_signed ? ez->vec_le_signed(a, b) : ez->vec_le_unsigned(a, b), y.at(0));
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if (cell->type == "$eq")
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ez->SET(ez->vec_eq(a, b), y.at(0));
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if (cell->type == "$ne")
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ez->SET(ez->vec_ne(a, b), y.at(0));
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if (cell->type == "$ge")
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ez->SET(is_signed ? ez->vec_ge_signed(a, b) : ez->vec_ge_unsigned(a, b), y.at(0));
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if (cell->type == "$gt")
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ez->SET(is_signed ? ez->vec_gt_signed(a, b) : ez->vec_gt_unsigned(a, b), y.at(0));
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for (size_t i = 1; i < y.size(); i++)
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ez->SET(0, y.at(0));
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return true;
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}
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if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
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std::vector<int> a = importSigSpec(cell->connections.at("\\A"), timestep);
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std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
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std::vector<int> y = importSigSpec(cell->connections.at("\\Y"), timestep);
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char shift_left = cell->type == "$shl" || cell->type == "$sshl";
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bool sign_extend = cell->type == "$sshr";
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while (y.size() < a.size())
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y.push_back(ez->literal());
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std::vector<int> tmp = a;
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for (size_t i = 0; i < b.size(); i++)
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{
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std::vector<int> tmp_shifted(tmp.size());
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for (size_t j = 0; j < tmp.size(); j++) {
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int idx = j + (1 << i) * (shift_left ? -1 : +1);
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tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE;
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}
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tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp);
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}
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ez->assume(ez->vec_eq(tmp, y));
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return true;
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}
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if (timestep > 0 && (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")) {
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if (timestep == 1) {
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initial_state.add((*sigmap)(cell->connections.at("\\Q")));
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} else {
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std::vector<int> d = importSigSpec(cell->connections.at("\\D"), timestep-1);
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std::vector<int> q = importSigSpec(cell->connections.at("\\Q"), timestep);
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ez->assume(ez->vec_eq(d, q));
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}
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return true;
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}
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// Unsupported internal cell types: $mul $div $mod $pow
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// .. and all sequential cells except $dff and $_DFF_[NP]_
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return false;
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}
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};
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#endif
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