mirror of https://github.com/YosysHQ/yosys.git
300 lines
9.9 KiB
C++
300 lines
9.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Wolf <claire@symbioticeda.com>
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* Copyright (C) 2019 Dan Ravensloft <dan.ravensloft@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthIntelALMPass : public ScriptPass {
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SynthIntelALMPass() : ScriptPass("synth_intel_alm", "synthesis for ALM-based Intel (Altera) FPGAs.") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_intel_alm [options]\n");
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log("\n");
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log("This command runs synthesis for ALM-based Intel FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -family <family>\n");
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log(" target one of:\n");
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log(" \"cyclonev\" - Cyclone V (default)\n");
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log(" \"cyclone10gx\" - Cyclone 10GX\n");
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log("\n");
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log(" -vqm <file>\n");
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log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
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log(" output file is omitted if this parameter is not specified. Implies -quartus.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis; useful for per-module area statistics\n");
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log("\n");
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log(" -quartus\n");
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log(" output a netlist using Quartus cells instead of MISTRAL_* cells\n");
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log("\n");
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log(" -dff\n");
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log(" pass DFFs to ABC to perform sequential logic optimisations (EXPERIMENTAL)\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -nolutram\n");
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log(" do not use LUT RAM cells in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use block RAM cells in output netlist\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not map multipliers to MISTRAL_MUL cells\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, family_opt, bram_type, vout_file;
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bool flatten, quartus, nolutram, nobram, dff, nodsp;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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family_opt = "cyclonev";
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bram_type = "m10k";
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vout_file = "";
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flatten = true;
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quartus = false;
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nolutram = false;
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nobram = false;
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dff = false;
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nodsp = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-family" && argidx + 1 < args.size()) {
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family_opt = args[++argidx];
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continue;
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}
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if (args[argidx] == "-top" && argidx + 1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
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quartus = true;
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vout_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx + 1 < args.size()) {
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size_t pos = args[argidx + 1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos + 1);
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continue;
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}
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if (args[argidx] == "-quartus") {
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quartus = true;
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continue;
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}
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if (args[argidx] == "-nolutram") {
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nolutram = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-dff") {
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dff = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (family_opt == "cyclonev") {
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bram_type = "m10k";
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} else if (family_opt == "cyclone10gx") {
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bram_type = "m20k";
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} else {
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log_cmd_error("Invalid family specified: '%s'\n", family_opt.c_str());
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}
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log_header(design, "Executing SYNTH_INTEL_ALM pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (help_mode) {
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family_opt = "<family>";
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bram_type = "<bram_type>";
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}
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if (check_label("begin")) {
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if (family_opt == "cyclonev")
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run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt.c_str()));
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// Misc and common cells
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run("read_verilog -lib +/intel/common/altpll_bb.v");
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run("read_verilog -lib +/intel_alm/common/megafunction_bb.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (check_label("coarse")) {
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run("proc");
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if (flatten || help_mode)
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run("flatten", "(skip if -noflatten)");
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run("tribuf -logic");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
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run("opt_expr");
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run("opt_clean");
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if (help_mode) {
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run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
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} else if (!nodsp) {
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// Cyclone V supports 9x9 multiplication, Cyclone 10 GX does not.
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=27 -D DSP_A_MINWIDTH=19 -D DSP_B_MINWIDTH=19 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL27X27");
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run("chtype -set $mul t:$__soft_mul");
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if (family_opt == "cyclonev") {
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=10 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL18X18");
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run("chtype -set $mul t:$__soft_mul");
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL9X9");
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run("chtype -set $mul t:$__soft_mul");
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} else if (family_opt == "cyclone10gx") {
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_SIGNEDONLY -D DSP_NAME=__MUL18X18");
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run("chtype -set $mul t:$__soft_mul");
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}
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}
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run("alumacc");
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run("techmap -map +/intel_alm/common/arith_alm_map.v -map +/intel_alm/common/dsp_map.v");
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run("opt");
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run("fsm");
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run("opt -fast");
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run("memory -nomap");
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run("opt_clean");
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}
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if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
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run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str()));
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run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
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}
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if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
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run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V / Cyclone 10GX)");
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}
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if (check_label("map_ffram")) {
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run("memory_map");
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run("opt -full");
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}
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if (check_label("map_ffs")) {
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run("techmap");
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run("dff2dffe");
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run("dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0");
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run("techmap -map +/intel_alm/common/dff_map.v");
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run("opt -full -undriven -mux_undef");
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run("clean -purge");
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}
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if (check_label("map_luts")) {
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run("techmap -map +/intel_alm/common/abc9_map.v");
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run(stringf("abc9 %s -maxlut 6 -W 200", help_mode ? "[-dff]" : dff ? "-dff" : ""));
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run("techmap -map +/intel_alm/common/abc9_unmap.v");
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run("techmap -map +/intel_alm/common/alm_map.v");
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run("opt -fast");
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run("autoname");
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run("clean");
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}
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if (check_label("check")) {
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run("hierarchy -check");
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run("stat");
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run("check");
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}
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if (check_label("quartus")) {
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if (quartus || help_mode) {
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// Quartus ICEs if you have a wire which has `[]` in its name,
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// which Yosys produces when building memories out of flops.
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run("rename -hide w:*[* w:*]*");
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// VQM mode does not support 'x, so replace those with zero.
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run("setundef -zero");
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// VQM mode does not support multi-bit constant assignments
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// (e.g. 2'b00 is an error), so as a workaround use references
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// to constant driver cells, which Quartus accepts.
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run("hilomap -singleton -hicell __MISTRAL_VCC Q -locell __MISTRAL_GND Q");
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// Rename from Yosys-internal MISTRAL_* cells to Quartus cells.
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run(stringf("techmap -D %s -map +/intel_alm/common/quartus_rename.v", family_opt.c_str()));
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}
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}
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if (check_label("vqm")) {
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if (!vout_file.empty() || help_mode) {
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run(stringf("write_verilog -attr2comment -defparam -nohex -decimal %s", help_mode ? "<file-name>" : vout_file.c_str()));
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}
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}
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}
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} SynthIntelALMPass;
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PRIVATE_NAMESPACE_END
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