mirror of https://github.com/YosysHQ/yosys.git
42 lines
944 B
Verilog
42 lines
944 B
Verilog
//-----------------------------------------------------
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// This is simple parity Program
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// Design Name : parity
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// File Name : parity.v
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// Function : This program shows how a verilog
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// primitive/module port connection are done
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// Coder : Deepak
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//-----------------------------------------------------
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module parity (
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a , // First input
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b , // Second input
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c , // Third Input
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d , // Fourth Input
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y // Parity output
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);
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// Input Declaration
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input a ;
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input b ;
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input c ;
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input d ;
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// Ouput Declaration
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output y ;
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// port data types
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wire a ;
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wire b ;
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wire c ;
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wire d ;
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wire y ;
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// Internal variables
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wire out_0 ;
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wire out_1 ;
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// Code starts Here
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xor u0 (out_0,a,b);
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xor u1 (out_1,c,d);
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xor u2 (y,out_0,out_1);
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endmodule // End Of Module parity
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