mirror of https://github.com/YosysHQ/yosys.git
15 lines
387 B
Verilog
15 lines
387 B
Verilog
module decoder (in,out);
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input [2:0] in;
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output [7:0] out;
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wire [7:0] out;
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assign out = (in == 3'b000 ) ? 8'b0000_0001 :
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(in == 3'b001 ) ? 8'b0000_0010 :
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(in == 3'b010 ) ? 8'b0000_0100 :
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(in == 3'b011 ) ? 8'b0000_1000 :
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(in == 3'b100 ) ? 8'b0001_0000 :
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(in == 3'b101 ) ? 8'b0010_0000 :
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(in == 3'b110 ) ? 8'b0100_0000 :
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(in == 3'b111 ) ? 8'b1000_0000 : 8'h00;
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endmodule
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