mirror of https://github.com/YosysHQ/yosys.git
30 lines
718 B
Verilog
30 lines
718 B
Verilog
//-----------------------------------------------------
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// Design Name : up_counter
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// File Name : up_counter.v
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// Function : Up counter
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// Coder : Deepak
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//-----------------------------------------------------
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module up_counter (
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out , // Output of the counter
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enable , // enable for counter
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clk , // clock Input
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reset // reset Input
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);
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//----------Output Ports--------------
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output [7:0] out;
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//------------Input Ports--------------
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input enable, clk, reset;
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//------------Internal Variables--------
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reg [7:0] out;
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//-------------Code Starts Here-------
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always @(posedge clk)
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if (reset) begin
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out <= 8'b0 ;
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end else if (enable) begin
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out <= out + 1;
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end
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endmodule
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