mirror of https://github.com/YosysHQ/yosys.git
21 lines
582 B
Verilog
21 lines
582 B
Verilog
//-----------------------------------------------------
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// Design Name : decoder_using_assign
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// File Name : decoder_using_assign.v
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// Function : decoder using assign
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module decoder_using_assign (
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binary_in , // 4 bit binary input
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decoder_out , // 16-bit out
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enable // Enable for the decoder
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);
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input [3:0] binary_in ;
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input enable ;
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output [15:0] decoder_out ;
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wire [15:0] decoder_out ;
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assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
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endmodule
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