mirror of https://github.com/YosysHQ/yosys.git
28 lines
986 B
Verilog
28 lines
986 B
Verilog
//-----------------------------------------------------
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// Design Name : clk_div
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// File Name : clk_div.v
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// Function : Divide by two counter
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module clk_div (clk_in, enable,reset, clk_out);
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// --------------Port Declaration-----------------------
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input clk_in ;
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input reset ;
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input enable ;
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output clk_out ;
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//--------------Port data type declaration-------------
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wire clk_in ;
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wire enable ;
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//--------------Internal Registers----------------------
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reg clk_out ;
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//--------------Code Starts Here-----------------------
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always @ (posedge clk_in)
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if (reset) begin
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clk_out <= 1'b0;
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end else if (enable) begin
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clk_out <= !clk_out ;
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end
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endmodule
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