yosys/passes
Eddie Hung 4cd8f02973 shregmap -tech xilinx to delete $shiftx for var length SRL 2019-03-19 15:05:08 -07:00
..
cmds Hotfix for 4c82ddf 2019-02-21 19:27:23 +01:00
equiv Fix equiv_opt indenting 2018-12-16 15:57:28 +01:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Only run derive on blackbox modules when ports have dynamic size 2019-03-02 12:36:46 -08:00
memory memory_collect: do not truncate 'x from \INIT. 2018-12-21 02:01:27 +00:00
opt Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327 2019-03-14 20:52:00 +01:00
pmgen Fix spelling in pmgen/README.md 2019-03-05 17:55:29 -08:00
proc proc_clean: fix critical typo. 2019-01-23 22:08:38 +00:00
sat Improve mix of src/wire/wirebit coverage in "mutate -list" 2019-03-16 00:55:46 +01:00
techmap shregmap -tech xilinx to delete $shiftx for var length SRL 2019-03-19 15:05:08 -07:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00