mirror of https://github.com/YosysHQ/yosys.git
76 lines
1.4 KiB
Plaintext
76 lines
1.4 KiB
Plaintext
state SigBit clock
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state bool clock_pol, clock_vld
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state SigSpec sigA, sigB, sigY
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match mul
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select mul->type.in($mul)
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select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
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select GetSize(mul->getPort(\Y)) > 10
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endmatch
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match ffA
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select ffA->type.in($dff)
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filter port(ffA, \Q) === port(mul, \A)
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optional
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endmatch
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code sigA clock clock_pol clock_vld
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sigA = port(mul, \A);
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if (ffA != nullptr) {
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sigA = port(ffA, \D);
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clock = port(ffA, \CLK).as_bit();
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clock_pol = param(ffA, \CLK_POLARITY).as_bool();
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clock_vld = true;
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}
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endcode
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match ffB
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select ffB->type.in($dff)
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filter port(ffB, \Q) === port(mul, \B)
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optional
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endmatch
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code sigB clock clok_pol clock_vld
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sigB = port(mul, \B);
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if (ffB != nullptr) {
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sigB = port(ffB, \D);
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SigBit c = port(ffB, \CLK).as_bit();
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bool cp = param(ffB, \CLK_POLARITY).as_bool();
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if (clock_vld && (c != clock || cp != clock_pol))
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reject;
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clock = c;
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clock_pol = cp;
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clock_vld = true;
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}
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endcode
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match ffY
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select ffY->type.in($dff)
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filter port(ffY, \D) === port(mul, \Y)
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optional
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endmatch
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code sigY clock clok_pol clock_vld
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sigY = port(mul, \Y);
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if (ffY != nullptr) {
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sigY = port(ffY, \D);
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SigBit c = port(ffY, \CLK).as_bit();
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bool cp = param(ffY, \CLK_POLARITY).as_bool();
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if (clock_vld && (c != clock || cp != clock_pol))
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reject;
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clock = c;
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clock_pol = cp;
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clock_vld = true;
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}
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accept;
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endcode
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