mirror of https://github.com/YosysHQ/yosys.git
292 lines
7.3 KiB
C++
292 lines
7.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef CONSTEVAL_H
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#define CONSTEVAL_H
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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struct ConstEval
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{
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RTLIL::Module *module;
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SigMap assign_map;
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SigMap values_map;
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SigPool stop_signals;
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SigSet<RTLIL::Cell*> sig2driver;
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std::set<RTLIL::Cell*> busy;
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std::vector<SigMap> stack;
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ConstEval(RTLIL::Module *module) : module(module), assign_map(module)
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{
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CellTypes ct;
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ct.setup_internals();
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ct.setup_stdcells();
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for (auto &it : module->cells_) {
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if (!ct.cell_known(it.second->type))
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continue;
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for (auto &it2 : it.second->connections())
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if (ct.cell_output(it.second->type, it2.first))
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sig2driver.insert(assign_map(it2.second), it.second);
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}
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}
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void clear()
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{
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values_map.clear();
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stop_signals.clear();
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}
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void push()
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{
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stack.push_back(values_map);
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}
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void pop()
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{
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values_map.swap(stack.back());
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stack.pop_back();
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}
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void set(RTLIL::SigSpec sig, RTLIL::Const value)
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{
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assign_map.apply(sig);
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#ifndef NDEBUG
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RTLIL::SigSpec current_val = values_map(sig);
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for (int i = 0; i < SIZE(current_val); i++)
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log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
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#endif
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values_map.add(sig, RTLIL::SigSpec(value));
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}
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void stop(RTLIL::SigSpec sig)
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{
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assign_map.apply(sig);
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stop_signals.add(sig);
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}
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bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)
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{
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RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
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log_assert(cell->hasPort("\\Y"));
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sig_y = values_map(assign_map(cell->getPort("\\Y")));
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if (sig_y.is_fully_const())
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return true;
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if (cell->hasPort("\\S")) {
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sig_s = cell->getPort("\\S");
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if (!eval(sig_s, undef, cell))
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return false;
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}
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if (cell->hasPort("\\A"))
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sig_a = cell->getPort("\\A");
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if (cell->hasPort("\\B"))
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sig_b = cell->getPort("\\B");
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if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_")
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{
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std::vector<RTLIL::SigSpec> y_candidates;
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int count_maybe_set_s_bits = 0;
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int count_set_s_bits = 0;
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for (int i = 0; i < sig_s.size(); i++)
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{
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RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
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RTLIL::SigSpec b_slice = sig_b.extract(sig_y.size()*i, sig_y.size());
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if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
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y_candidates.push_back(b_slice);
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if (s_bit == RTLIL::State::S1 || s_bit == RTLIL::State::Sx)
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count_maybe_set_s_bits++;
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if (s_bit == RTLIL::State::S1)
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count_set_s_bits++;
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}
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if (count_set_s_bits == 0)
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y_candidates.push_back(sig_a);
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std::vector<RTLIL::Const> y_values;
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log_assert(y_candidates.size() > 0);
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for (auto &yc : y_candidates) {
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if (!eval(yc, undef, cell))
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return false;
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y_values.push_back(yc.as_const());
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}
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if (y_values.size() > 1)
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{
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std::vector<RTLIL::State> master_bits = y_values.at(0).bits;
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for (size_t i = 1; i < y_values.size(); i++) {
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std::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;
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log_assert(master_bits.size() == slave_bits.size());
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for (size_t j = 0; j < master_bits.size(); j++)
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if (master_bits[j] != slave_bits[j])
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master_bits[j] = RTLIL::State::Sx;
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}
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set(sig_y, RTLIL::Const(master_bits));
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}
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else
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set(sig_y, y_values.front());
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}
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else if (cell->type == "$alu")
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{
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bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
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bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
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RTLIL::SigSpec sig_ci = cell->getPort("\\CI");
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RTLIL::SigSpec sig_bi = cell->getPort("\\BI");
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if (!eval(sig_a, undef, cell))
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return false;
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if (!eval(sig_b, undef, cell))
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return false;
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if (!eval(sig_ci, undef, cell))
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return false;
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if (!eval(sig_bi, undef, cell))
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return false;
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RTLIL::SigSpec sig_x = cell->getPort("\\X");
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RTLIL::SigSpec sig_co = cell->getPort("\\CO");
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bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
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sig_a.extend(SIZE(sig_y), signed_a);
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sig_b.extend(SIZE(sig_y), signed_b);
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bool carry = sig_ci[0] == RTLIL::S1;
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bool b_inv = sig_bi[0] == RTLIL::S1;
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for (int i = 0; i < SIZE(sig_y); i++)
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{
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RTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };
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if (!x_inputs.is_fully_def()) {
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set(sig_x[i], RTLIL::Sx);
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} else {
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bool bit_a = sig_a[i] == RTLIL::S1;
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bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv;
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bool bit_x = bit_a != bit_b;
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set(sig_x[i], bit_x ? RTLIL::S1 : RTLIL::S0);
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}
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if (any_input_undef) {
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set(sig_y[i], RTLIL::Sx);
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set(sig_co[i], RTLIL::Sx);
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} else {
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bool bit_a = sig_a[i] == RTLIL::S1;
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bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv;
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bool bit_y = (bit_a != bit_b) != carry;
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carry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);
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set(sig_y[i], bit_y ? RTLIL::S1 : RTLIL::S0);
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set(sig_co[i], carry ? RTLIL::S1 : RTLIL::S0);
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}
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}
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}
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else
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{
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RTLIL::SigSpec sig_c, sig_d;
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if (cell->type.in("$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_")) {
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if (cell->hasPort("\\C"))
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sig_c = cell->getPort("\\C");
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if (cell->hasPort("\\D"))
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sig_d = cell->getPort("\\D");
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}
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if (sig_a.size() > 0 && !eval(sig_a, undef, cell))
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return false;
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if (sig_b.size() > 0 && !eval(sig_b, undef, cell))
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return false;
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if (sig_c.size() > 0 && !eval(sig_c, undef, cell))
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return false;
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if (sig_d.size() > 0 && !eval(sig_d, undef, cell))
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return false;
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set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(),
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sig_c.as_const(), sig_d.as_const()));
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}
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return true;
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}
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bool eval(RTLIL::SigSpec &sig, RTLIL::SigSpec &undef, RTLIL::Cell *busy_cell = NULL)
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{
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assign_map.apply(sig);
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values_map.apply(sig);
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if (sig.is_fully_const())
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return true;
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if (stop_signals.check_any(sig)) {
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undef = stop_signals.extract(sig);
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return false;
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}
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if (busy_cell) {
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if (busy.count(busy_cell) > 0) {
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undef = sig;
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return false;
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}
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busy.insert(busy_cell);
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}
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std::set<RTLIL::Cell*> driver_cells;
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sig2driver.find(sig, driver_cells);
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for (auto cell : driver_cells) {
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if (!eval(cell, undef)) {
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if (busy_cell)
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busy.erase(busy_cell);
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return false;
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}
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}
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if (busy_cell)
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busy.erase(busy_cell);
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values_map.apply(sig);
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if (sig.is_fully_const())
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return true;
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for (auto &c : sig.chunks())
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if (c.wire != NULL)
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undef.append(c);
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return false;
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}
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bool eval(RTLIL::SigSpec &sig)
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{
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RTLIL::SigSpec undef;
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return eval(sig, undef);
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}
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};
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#endif
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