Clifford Wolf 18609f3df8 Merge branch 'master' of github.com:cliffordwolf/yosys		2017-09-01 12:35:09 +02:00
..
cmds	More intuitive handling of "cd .." for singleton modules	2017-08-19 00:15:12 +02:00
equiv	Fix equiv_simple, old behavior now available with "equiv_simple -short"	2017-04-28 18:57:53 +02:00
fsm	Remove some dead code from fsm_map	2017-08-21 15:02:16 +02:00
hierarchy	Rename "singleton" pass to "uniquify"	2017-08-20 12:31:50 +02:00
memory	Typo fix.	2016-09-08 10:57:16 +03:00
opt	Don't track , ... contradictions through x/z-bits	2017-08-25 16:18:17 +02:00
proc	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
sat	Rename "singleton" pass to "uniquify"	2017-08-20 12:31:50 +02:00
techmap	Merge branch 'master' of github.com:cliffordwolf/yosys	2017-09-01 12:35:09 +02:00
tests	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00