Miodrag Milanović d7f7227ce8 Merge pull request #3185 from YosysHQ/micko/co_sim ... Add co-simulation in sim pass		2022-02-07 16:36:43 +01:00
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cmds	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
equiv	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
fsm	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
hierarchy	verilog: use derived module info to elaborate cell connections	2021-10-25 18:25:50 -07:00
memory	memory_bram: Make use of new mem emulation functions to map more RAMs.	2022-01-27 19:31:27 +01:00
opt	opt_reduce: Add $bmux and $demux optimization patterns.	2022-01-30 03:37:52 +01:00
pmgen	Update comment	2022-02-02 03:21:09 +01:00
proc	proc_dff: Emit $aldff.	2021-10-27 14:14:24 +02:00
sat	Merge pull request #3185 from YosysHQ/micko/co_sim	2022-02-07 16:36:43 +01:00
techmap	Correct a typo in the manual	2022-02-02 21:14:38 +10:00
tests	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00