yosys/techlibs/ice40
Eddie Hung 91c3afcab7 Use nonblocking 2019-04-23 13:42:06 -07:00
..
tests Bugfix in ice40_dsp 2019-02-21 13:28:46 +01:00
.gitignore Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
Makefile.inc Also update Makefile.inc 2019-04-18 09:58:34 -07:00
abc_hx.box Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
abc_hx.lut Fix rename 2019-04-18 09:04:34 -07:00
abc_lp.box Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
abc_lp.lut Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
abc_u.box Make SB_DFF whitebox 2019-04-19 08:36:38 -07:00
abc_u.lut Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
arith_map.v Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 2019-04-17 11:10:20 -07:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_init.py Switched to Python 3 2015-08-22 09:59:33 +02:00
brams_map.v ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 2019-02-28 16:23:40 -08:00
cells_map.v Map to SB_LUT4 from fastest input first 2019-04-17 13:01:17 -07:00
cells_sim.v Use nonblocking 2019-04-23 13:42:06 -07:00
ice40_braminit.cc Fix typo in ice40_braminit help msg 2019-03-09 13:24:55 -08:00
ice40_ffinit.cc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
ice40_ffssr.cc ice40: Honor the "dont_touch" attribute in FFSSR pass 2018-12-08 22:46:28 +01:00
ice40_opt.cc Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 2019-04-17 11:10:20 -07:00
ice40_unlut.cc Extract ice40_unlut pass from ice40_opt. 2018-12-05 16:30:24 +00:00
latches_map.v Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
synth_ice40.cc Convert to use #945 2019-04-21 15:19:02 -07:00