mirror of https://github.com/YosysHQ/yosys.git
337 lines
8.6 KiB
Plaintext
337 lines
8.6 KiB
Plaintext
pattern xilinx_dsp_cascade
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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udata <vector<std::tuple<Cell*,int,int,int>>> chain longest_chain
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state <Cell*> next
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state <SigSpec> clock
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state <int> AREG BREG
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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code
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#define MAX_DSP_CASCADE 20
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endcode
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match first
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select first->type.in(\DSP48E1)
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select port(first, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("000")
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select nusers(port(first, \PCOUT, SigSpec())) <= 1
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endmatch
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code
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longest_chain.clear();
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chain.emplace_back(first, -1, -1, -1);
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subpattern(tail);
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finally
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chain.pop_back();
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log_assert(chain.empty());
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if (GetSize(longest_chain) > 1) {
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Cell *dsp = std::get<0>(longest_chain.front());
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Cell *dsp_pcin;
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int P, AREG, BREG;
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for (int i = 1; i < GetSize(longest_chain); i++) {
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std::tie(dsp_pcin,P,AREG,BREG) = longest_chain[i];
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if (i % MAX_DSP_CASCADE > 0) {
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if (P >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 48);
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dsp_pcin->setPort(ID(C), Const(0, 48));
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dsp_pcin->setPort(ID(PCIN), cascade);
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dsp->setPort(ID(PCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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SigSpec opmode = port(dsp_pcin, \OPMODE, Const(0, 7));
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if (P == 17)
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opmode[6] = State::S1;
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else if (P == 0)
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opmode[6] = State::S0;
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else log_abort();
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opmode[5] = State::S0;
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opmode[4] = State::S1;
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dsp_pcin->setPort(\OPMODE, opmode);
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log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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if (AREG >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 30);
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dsp_pcin->setPort(ID(A), Const(0, 30));
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dsp_pcin->setPort(ID(ACIN), cascade);
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dsp->setPort(ID(ACOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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dsp->setParam(ID(ACASCREG), AREG);
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dsp_pcin->setParam(ID(A_INPUT), Const("CASCADE"));
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log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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if (BREG >= 0) {
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Wire *cascade = module->addWire(NEW_ID, 18);
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dsp_pcin->setPort(ID(B), Const(0, 18));
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dsp_pcin->setPort(ID(BCIN), cascade);
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dsp->setPort(ID(BCOUT), cascade);
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add_siguser(cascade, dsp_pcin);
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add_siguser(cascade, dsp);
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dsp->setParam(ID(BCASCREG), BREG);
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dsp_pcin->setParam(ID(B_INPUT), Const("CASCADE"));
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log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
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}
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}
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else {
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log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
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}
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dsp = dsp_pcin;
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}
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accept;
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}
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endcode
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// ------------------------------------------------------------------
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subpattern tail
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arg first
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arg next
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match nextP
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select nextP->type.in(\DSP48E1)
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select !param(nextP, \CREG, State::S1).as_bool()
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select port(nextP, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(nextP, \C, SigSpec())) > 1
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select nusers(port(nextP, \PCIN, SigSpec())) == 0
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index <SigBit> port(nextP, \C)[0] === port(std::get<0>(chain.back()), \P)[0]
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semioptional
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endmatch
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match nextP_shift17
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if !nextP
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select nextP_shift17->type.in(\DSP48E1)
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select !param(nextP_shift17, \CREG, State::S1).as_bool()
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select port(nextP_shift17, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("011")
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select nusers(port(nextP_shift17, \C, SigSpec())) > 1
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select nusers(port(nextP_shift17, \PCIN, SigSpec())) == 0
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index <SigBit> port(nextP_shift17, \C)[0] === port(std::get<0>(chain.back()), \P)[17]
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semioptional
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endmatch
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code next
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next = nextP;
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if (!nextP)
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next = nextP_shift17;
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if (next) {
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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}
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endcode
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code argQ clock AREG
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AREG = -1;
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if (next) {
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Cell *prev = std::get<0>(chain.back());
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if (param(prev, \AREG, 2).as_int() > 0 &&
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param(next, \AREG, 2).as_int() > 0 &&
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param(next, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" &&
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port(next, \ACIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \ACOUT, SigSpec())) <= 1) {
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argQ = unextend(port(next, \A));
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clock = port(prev, \CLK);
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subpattern(in_dffe);
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if (dff) {
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if (!dffrstmux && port(prev, \RSTA, State::S0) != State::S0)
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goto reject_AREG;
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if (dffrstmux && port(dffrstmux, \S) != port(prev, \RSTA, State::S0))
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goto reject_AREG;
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if (!dffcemux && port(prev, \CEA2, State::S0) != State::S0)
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goto reject_AREG;
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if (dffcemux && port(dffcemux, \S) != port(prev, \CEA2, State::S0))
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goto reject_AREG;
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if (dffD == unextend(port(prev, \A)))
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AREG = 1;
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reject_AREG: ;
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}
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}
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}
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endcode
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code argQ clock BREG
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BREG = -1;
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if (next) {
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Cell *prev = std::get<0>(chain.back());
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if (param(prev, \BREG, 2).as_int() > 0 &&
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param(next, \BREG, 2).as_int() > 0 &&
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param(next, \B_INPUT, Const("DIRECT")).decode_string() == "DIRECT" &&
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port(next, \BCIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \BCOUT, SigSpec())) <= 1) {
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argQ = unextend(port(next, \B));
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clock = port(prev, \CLK);
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subpattern(in_dffe);
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if (dff) {
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if (!dffrstmux && port(prev, \RSTB, State::S0) != State::S0)
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goto reject_BREG;
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if (dffrstmux && port(dffrstmux, \S) != port(prev, \RSTB, State::S0))
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goto reject_BREG;
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if (!dffcemux && port(prev, \CEB2, State::S0) != State::S0)
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goto reject_BREG;
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if (dffcemux && port(dffcemux, \S) != port(prev, \CEB2, State::S0))
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goto reject_BREG;
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if (dffD == unextend(port(prev, \B)))
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BREG = 1;
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reject_BREG: ;
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}
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}
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}
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endcode
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code
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if (next) {
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chain.emplace_back(next, nextP_shift17 ? 17 : nextP ? 0 : -1, AREG, BREG);
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SigSpec sigC = unextend(port(next, \C));
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// TODO: Cannot use 'reject' since semioptional
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if (nextP_shift17) {
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if (GetSize(sigC)+17 <= GetSize(port(std::get<0>(chain.back()), \P)) &&
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port(std::get<0>(chain.back()), \P).extract(17, GetSize(sigC)) != sigC)
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subpattern(tail);
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}
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else {
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if (GetSize(sigC) <= GetSize(port(std::get<0>(chain.back()), \P)) &&
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port(std::get<0>(chain.back()), \P).extract(0, GetSize(sigC)) != sigC)
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subpattern(tail);
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}
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} else {
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if (GetSize(chain) > GetSize(longest_chain))
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longest_chain = chain;
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}
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finally
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if (next)
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chain.pop_back();
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endcode
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// #######################
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subpattern in_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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if (!c.wire)
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reject;
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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}
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endcode
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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// Check that the rest of argQ is present
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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set ffoffset offset
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endmatch
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code argQ argD
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{
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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argD = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, argD);
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// Only search for ffrstmux if dffD only
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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}
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endcode
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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index <SigSpec> port(ffrstmux, \Y) === argD
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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define <bool> pol (BA == \B)
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set ffrstpol pol
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semioptional
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endmatch
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code argD
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if (ffrstmux) {
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
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argD = port(ffrstmux, ffrstpol ? \A : \B);
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dffD.replace(port(ffrstmux, \Y), argD);
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// Only search for ffcemux if argQ has at
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// least 3 users (ff, <upstream>, ffrstmux) and
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// dffD only has two (ff, ffrstmux)
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if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
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argD = SigSpec();
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}
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else
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dffrstmux = nullptr;
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endcode
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match ffcemux
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if !argD.empty()
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select ffcemux->type.in($mux)
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index <SigSpec> port(ffcemux, \Y) === argD
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(ffcemux, AB) === argQ
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define <bool> pol (AB == \A)
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set ffcepol pol
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semioptional
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endmatch
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code argD
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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argD = port(ffcemux, ffcepol ? \B : \A);
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dffD.replace(port(ffcemux, \Y), argD);
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}
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else
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dffcemux = nullptr;
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endcode
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