mirror of https://github.com/YosysHQ/yosys.git
38 lines
535 B
Plaintext
38 lines
535 B
Plaintext
ram block \RAM_WREN {
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abits 4;
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init none;
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ifdef NO_BYTE {
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# single enable signal
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widths 4 8 global;
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} else ifdef W4_B4 {
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widths 4 global;
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byte 4;
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} else ifdef W8_B4 {
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widths 8 global;
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option "BYTESIZE" 4 {
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byte 4;
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}
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} else ifdef W8_B8 {
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width 8;
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byte 8;
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} else ifdef W16_B4 {
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widths 16 global;
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option "BYTESIZE" 4 {
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byte 4;
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}
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} else ifdef W64_B8 {
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widths 64 global;
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option "BYTESIZE" 8 {
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byte 8;
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}
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}
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port srsw "A" {
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clock posedge;
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ifdef WRBE_SEPARATE {
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wrbe_separate;
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}
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}
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}
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