mirror of https://github.com/YosysHQ/yosys.git
69 lines
1.7 KiB
Verilog
69 lines
1.7 KiB
Verilog
module RAM_9b1B (
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input PORT_R_CLK,
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input [6:0] PORT_R_ADDR,
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output reg [PORT_R_WIDTH-1:0] PORT_R_RD_DATA,
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input PORT_W_CLK,
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input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN,
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input [6:0] PORT_W_ADDR,
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA
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);
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parameter INIT = 0;
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parameter OPTION_INIT = "UNDEFINED";
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parameter PORT_R_WIDTH = 9;
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parameter PORT_W_WIDTH = 9;
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parameter PORT_R_CLK_POL = 0;
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parameter PORT_W_CLK_POL = 0;
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parameter PORT_W_WR_EN_WIDTH = 1;
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reg [8:0] mem [0:15];
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integer i;
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initial
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for (i = 0; i < 16; i += 1)
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case (OPTION_INIT)
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"NONE": mem[i] = mem[i]; //?
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"ZERO": mem[i] = 9'h0;
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"ANY": mem[i] = INIT[i*9+:9];
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"NO_UNDEF": mem[i] = INIT[i*9+:9];
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"UNDEFINED": mem[i] = 9'hx;
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endcase
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wire [3:0] addr_r;
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assign addr_r = PORT_R_ADDR[6:3];
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reg [17:0] mem_read;
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reg [2:0] subaddr_r;
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always @(negedge (PORT_R_CLK ^ PORT_R_CLK_POL)) begin
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subaddr_r <= PORT_R_ADDR[2:0];
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mem_read[8:0] <= mem[addr_r];
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if (PORT_R_WIDTH == 18)
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mem_read[17:9] <= mem[addr_r + 1];
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end
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always @(mem_read, subaddr_r) begin
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case (PORT_R_WIDTH)
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18: PORT_R_RD_DATA <= mem_read;
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9: PORT_R_RD_DATA <= mem_read[8:0];
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4: PORT_R_RD_DATA <= mem_read[subaddr_r[2]*4+:4];
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2: PORT_R_RD_DATA <= mem_read[subaddr_r[2:1]*2+:2];
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1: PORT_R_RD_DATA <= mem_read[subaddr_r];
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endcase
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end
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wire [3:0] addr_w;
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assign addr_w = PORT_W_ADDR[6:3];
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always @(negedge (PORT_W_CLK ^ PORT_W_CLK_POL)) begin
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if (PORT_W_WR_EN[0])
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case (PORT_W_WIDTH)
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18,
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9: mem[addr_w] <= PORT_W_WR_DATA[8:0];
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4: mem[addr_w][PORT_W_ADDR[2]*4+:4] <= PORT_W_WR_DATA;
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2: mem[addr_w][PORT_W_ADDR[2:1]*2+:2] <= PORT_W_WR_DATA;
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1: mem[addr_w][PORT_W_ADDR[2:0]] <= PORT_W_WR_DATA;
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endcase
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if (PORT_W_WR_EN[1])
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mem[addr_w + 1] <= PORT_W_WR_DATA[17:9];
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end
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endmodule
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