This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
aaa5347494
yosys
/
tests
/
errors
/
syntax_err06.v
7 lines
56 B
Verilog
Raw
Blame
History
module
a
;
initial
begin
:
label1
end
:
label2
endmodule
Reference in New Issue
View Git Blame
Copy Permalink