yosys/frontends/verilog
Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
..
.gitignore Updated .gitignore file for ilang and verilog frontends 2014-10-15 01:14:38 +02:00
Makefile.inc Adjust makefiles to work with out-of-tree builds 2015-08-12 15:04:44 +02:00
const2ast.cc Fixed segfault on invalid verilog constant 1'b_ 2015-09-22 08:13:09 +02:00
preproc.cc Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
verilog_frontend.cc Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
verilog_frontend.h Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
verilog_lexer.l Removed $predict again 2016-08-28 21:35:33 +02:00
verilog_parser.y Added $anyseq cell type 2016-10-14 15:24:03 +02:00