mirror of https://github.com/YosysHQ/yosys.git
209 lines
6.3 KiB
C++
209 lines
6.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
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{
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if (label == run_from)
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active = true;
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if (label == run_to)
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active = false;
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return active;
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}
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struct SynthXilinxPass : public Pass {
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SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_xilinx [options]\n");
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log("\n");
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log("This command runs synthesis for Xilinx FPGAs. This command does not operate on\n");
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log("partly selected designs. At the moment this command creates netlists that are\n");
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log("compatible with 7-Series Xilinx devices.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified edif file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -flatten\n");
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log(" flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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log("\n");
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log(" begin:\n");
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log(" read_verilog -lib +/xilinx/cells_sim.v\n");
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log(" hierarchy -check -top <top>\n");
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log("\n");
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log(" flatten: (only if -flatten)\n");
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log(" proc\n");
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log(" flatten\n");
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log("\n");
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log(" coarse:\n");
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log(" synth -run coarse\n");
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log(" dff2dffe\n");
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log("\n");
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log(" bram:\n");
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log(" memory_bram -rules +/xilinx/brams.txt\n");
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log(" techmap -map +/xilinx/brams_map.v\n");
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log("\n");
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log(" fine:\n");
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log(" opt -fast -full\n");
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log(" memory_map\n");
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log(" opt -full\n");
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log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
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log(" opt -fast\n");
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log("\n");
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log(" map_luts:\n");
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log(" abc -lut 5:8 [-dff]\n");
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log(" clean\n");
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log("\n");
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log(" map_cells:\n");
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log(" techmap -map +/xilinx/cells_map.v\n");
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log(" clean\n");
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log("\n");
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log(" edif:\n");
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log(" write_edif synth.edif\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string top_module = "top";
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std::string arch_name = "spartan6";
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std::string edif_file;
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std::string run_from, run_to;
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bool flatten = false;
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bool retime = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_module = args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This comannd only operates on fully selected designs!\n");
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bool active = run_from.empty();
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log_header("Executing SYNTH_XILINX pass.\n");
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log_push();
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if (check_label(active, run_from, run_to, "begin"))
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{
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Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
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Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
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}
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if (flatten && check_label(active, run_from, run_to, "flatten"))
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{
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Pass::call(design, "proc");
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Pass::call(design, "flatten");
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}
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if (check_label(active, run_from, run_to, "coarse"))
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{
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Pass::call(design, "synth -run coarse");
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Pass::call(design, "dff2dffe");
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}
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if (check_label(active, run_from, run_to, "bram"))
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{
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Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
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Pass::call(design, "techmap -map +/xilinx/brams_map.v");
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}
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if (check_label(active, run_from, run_to, "fine"))
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{
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Pass::call(design, "opt -fast -full");
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Pass::call(design, "memory_map");
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Pass::call(design, "opt -full");
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Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
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Pass::call(design, "opt -fast");
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}
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if (check_label(active, run_from, run_to, "map_luts"))
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{
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Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : ""));
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Pass::call(design, "clean");
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}
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if (check_label(active, run_from, run_to, "map_cells"))
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{
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Pass::call(design, "techmap -map +/xilinx/cells_map.v");
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Pass::call(design, "clean");
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}
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if (check_label(active, run_from, run_to, "edif"))
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{
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if (!edif_file.empty())
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Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
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}
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log_pop();
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}
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} SynthXilinxPass;
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PRIVATE_NAMESPACE_END
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