mirror of https://github.com/YosysHQ/yosys.git
513 lines
16 KiB
C++
513 lines
16 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void break_scc(RTLIL::Module *module)
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{
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// For every unique SCC found, (arbitrarily) find the first
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// cell in the component, and convert all wires driven by
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// its output ports into a new PO, and drive its previous
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// sinks with a new PI
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pool<RTLIL::Const> ids_seen;
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for (auto cell : module->selected_cells()) {
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auto it = cell->attributes.find(ID(abc9_scc_id));
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if (it == cell->attributes.end())
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continue;
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auto r = ids_seen.insert(it->second);
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cell->attributes.erase(it);
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if (!r.second)
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continue;
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for (auto &c : cell->connections_) {
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if (c.second.is_fully_const()) continue;
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if (cell->output(c.first)) {
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SigBit b = c.second.as_bit();
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Wire *w = b.wire;
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if (w->port_input) {
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// In this case, hopefully the loop break has been already created
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// Get the non-prefixed wire
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Wire *wo = module->wire(stringf("%s.abco", b.wire->name.c_str()));
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log_assert(wo != nullptr);
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log_assert(wo->port_output);
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log_assert(b.offset < GetSize(wo));
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c.second = RTLIL::SigBit(wo, b.offset);
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}
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else {
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// Create a new output/input loop break
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w->port_input = true;
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w = module->wire(stringf("%s.abco", w->name.c_str()));
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if (!w) {
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w = module->addWire(stringf("%s.abco", b.wire->name.c_str()), GetSize(b.wire));
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w->port_output = true;
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}
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else {
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log_assert(w->port_input);
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log_assert(b.offset < GetSize(w));
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}
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w->set_bool_attribute(ID(abc9_scc_break));
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c.second = RTLIL::SigBit(w, b.offset);
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}
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}
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}
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}
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module->fixup_ports();
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}
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void unbreak_scc(RTLIL::Module *module)
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{
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// Now 'unexpose' those wires by undoing
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// the expose operation -- remove them from PO/PI
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// and re-connecting them back together
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for (auto wire : module->wires()) {
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auto it = wire->attributes.find(ID(abc9_scc_break));
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if (it != wire->attributes.end()) {
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wire->attributes.erase(it);
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log_assert(wire->port_output);
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wire->port_output = false;
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std::string name = wire->name.str();
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RTLIL::Wire *i_wire = module->wire(name.substr(0, GetSize(name) - 5));
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log_assert(i_wire);
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log_assert(i_wire->port_input);
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i_wire->port_input = false;
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module->connect(i_wire, wire);
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}
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}
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module->fixup_ports();
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}
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void prep_dff(RTLIL::Module *module)
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{
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auto design = module->design;
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log_assert(design);
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SigMap assign_map(module);
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typedef SigSpec clkdomain_t;
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dict<clkdomain_t, int> clk_to_mergeability;
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//if (dff_mode)
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for (auto cell : module->selected_cells()) {
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if (cell->type != "$__ABC9_FF_")
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continue;
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Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
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if (abc9_clock_wire == NULL)
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log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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SigSpec abc9_clock = assign_map(abc9_clock_wire);
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clkdomain_t key(abc9_clock);
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auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
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auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
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log_assert(r2.second);
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Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
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if (abc9_init_wire == NULL)
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log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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log_assert(GetSize(abc9_init_wire) == 1);
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SigSpec abc9_init = assign_map(abc9_init_wire);
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if (!abc9_init.is_fully_const())
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log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
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log_assert(r2.second);
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}
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//else
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// for (auto cell : module->selected_cells()) {
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// auto inst_module = design->module(cell->type);
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// if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
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// continue;
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// cell->set_bool_attribute("\\abc9_keep");
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// }
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RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
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if (holes_module) {
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dict<SigSig, SigSig> replace;
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for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
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auto cell = it->second;
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if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
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SigBit D = cell->getPort("\\D");
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SigBit Q = cell->getPort("\\Q");
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// Remove the DFF cell from what needs to be a combinatorial box
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it = holes_module->cells_.erase(it);
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Wire *port;
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if (GetSize(Q.wire) == 1)
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port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
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else
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port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
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log_assert(port);
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// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
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// in order to extract the combinatorial control logic that feeds the box
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// (i.e. clock enable, synchronous reset, etc.)
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replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
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// Since `flatten` above would have created wires named "<cell>.Q",
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// extract the pre-techmap cell name
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auto pos = Q.wire->name.str().rfind(".");
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log_assert(pos != std::string::npos);
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IdString driver = Q.wire->name.substr(0, pos);
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// And drive the signal that was previously driven by "DFF.Q" (typically
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// used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
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// wire (which itself is driven an input port) we inserted above
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Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
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log_assert(currQ);
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holes_module->connect(Q, currQ);
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}
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else
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++it;
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}
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for (auto &conn : holes_module->connections_) {
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auto it = replace.find(conn);
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if (it != replace.end())
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conn = it->second;
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}
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}
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}
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void prep_holes(RTLIL::Module *module)
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{
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auto design = module->design;
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log_assert(design);
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SigMap sigmap(module);
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// TODO: Speed up toposort -- ultimately we care about
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc9_box_seen = false;
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for (auto cell : module->selected_cells()) {
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if (cell->type == "$_NOT_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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continue;
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}
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit B = sigmap(cell->getPort("\\B").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_users[B].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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continue;
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}
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if (cell->type == "$__ABC9_FF_")
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continue;
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RTLIL::Module* inst_module = design->module(cell->type);
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if (inst_module) {
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if (!inst_module->attributes.count("\\abc9_box_id") || cell->get_bool_attribute("\\abc9_keep"))
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continue;
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_input && !port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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abc9_box_seen = true;
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toposort.node(cell->name);
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}
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}
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if (!abc9_box_seen)
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return;
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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#if 0
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toposort.analyze_loops = true;
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#endif
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bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
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#if 0
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d\n", i++);
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for (auto cell_name : it) {
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auto cell = module->cell(cell_name);
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log_assert(cell);
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log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
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}
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}
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#endif
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log_assert(no_loops);
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vector<Cell*> box_list;
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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log_assert(cell);
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RTLIL::Module* box_module = design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc9_box_id")
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|| cell->get_bool_attribute("\\abc9_keep"))
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continue;
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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// Fully pad all unused input connections of this box cell with S0
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// Fully pad all undriven output connections of this box cell with anonymous wires
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire* w = box_module->wire(port_name);
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log_assert(w);
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auto it = cell->connections_.find(port_name);
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if (w->port_input) {
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RTLIL::SigSpec rhs;
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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}
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else {
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rhs = RTLIL::SigSpec(State::S0, GetSize(w));
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cell->setPort(port_name, rhs);
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}
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}
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if (w->port_output) {
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RTLIL::SigSpec rhs;
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auto it = cell->connections_.find(w->name);
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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}
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else {
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Wire *wire = module->addWire(NEW_ID, GetSize(w));
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if (blackbox)
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wire->set_bool_attribute(ID(abc9_padding));
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rhs = wire;
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cell->setPort(port_name, rhs);
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}
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}
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}
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cell->attributes["\\abc9_box_order"] = box_list.size();
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box_list.emplace_back(cell);
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}
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log_assert(!box_list.empty());
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RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
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log_assert(holes_module);
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holes_module->set_bool_attribute("\\abc9_holes");
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dict<IdString, Cell*> cell_cache;
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dict<IdString, std::vector<IdString>> box_ports;
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int port_id = 1;
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for (auto cell : box_list) {
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RTLIL::Module* orig_box_module = design->module(cell->type);
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log_assert(orig_box_module);
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IdString derived_name = orig_box_module->derive(design, cell->parameters);
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RTLIL::Module* box_module = design->module(derived_name);
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if (box_module->has_processes())
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Pass::call_on_module(design, box_module, "proc");
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int box_inputs = 0;
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auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
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Cell *holes_cell = r.first->second;
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if (r.second && box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, cell->type);
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holes_cell->parameters = cell->parameters;
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r.first->second = holes_cell;
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}
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auto r2 = box_ports.insert(cell->type);
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if (r2.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
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carry_out = port_name;
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}
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}
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else
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r2.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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r2.first->second.push_back(carry_in);
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r2.first->second.push_back(carry_out);
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}
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}
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for (const auto &port_name : box_ports.at(cell->type)) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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RTLIL::Wire *holes_wire;
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RTLIL::SigSpec port_sig;
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if (w->port_input)
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for (int i = 0; i < GetSize(w); i++) {
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box_inputs++;
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holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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if (holes_cell)
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port_sig.append(holes_wire);
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}
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if (w->port_output)
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for (int i = 0; i < GetSize(w); i++) {
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if (GetSize(w) == 1)
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holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
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else
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holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
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holes_wire->port_output = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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if (holes_cell)
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port_sig.append(holes_wire);
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else
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holes_module->connect(holes_wire, State::S0);
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}
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if (!port_sig.empty()) {
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if (r.second)
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holes_cell->setPort(w->name, port_sig);
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else
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holes_module->connect(holes_cell->getPort(w->name), port_sig);
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}
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}
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// For flops only, create an extra 1-bit input that drives a new wire
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// called "<cell>.$abc9_currQ" that is used below
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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log_assert(holes_cell);
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box_inputs++;
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Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
|
|
holes_module->connect(w, holes_wire);
|
|
}
|
|
}
|
|
}
|
|
|
|
struct Abc9OpsPass : public Pass {
|
|
Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" abc9_ops [options] [selection]\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
|
|
|
|
bool break_scc_mode = false;
|
|
bool unbreak_scc_mode = false;
|
|
bool prep_dff_mode = false;
|
|
bool prep_holes_mode = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
std::string arg = args[argidx];
|
|
if (arg == "-break_scc") {
|
|
break_scc_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-unbreak_scc") {
|
|
unbreak_scc_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-prep_dff") {
|
|
prep_dff_mode = true;
|
|
continue;
|
|
}
|
|
if (arg == "-prep_holes") {
|
|
prep_holes_mode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
for (auto mod : design->selected_modules()) {
|
|
if (mod->get_blackbox_attribute())
|
|
continue;
|
|
if (mod->get_bool_attribute("\\abc9_holes"))
|
|
continue;
|
|
|
|
if (mod->processes.size() > 0) {
|
|
log("Skipping module %s as it contains processes.\n", log_id(mod));
|
|
continue;
|
|
}
|
|
|
|
if (break_scc_mode)
|
|
break_scc(mod);
|
|
if (unbreak_scc_mode)
|
|
unbreak_scc(mod);
|
|
if (prep_dff_mode)
|
|
prep_dff(mod);
|
|
if (prep_holes_mode)
|
|
prep_holes(mod);
|
|
}
|
|
}
|
|
} Abc9OpsPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|