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35 lines
1.2 KiB
ReStructuredText
35 lines
1.2 KiB
ReStructuredText
Synthesis in detail
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-------------------
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Synthesis can generally be broken down into coarse-grain synthesis, and
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fine-grain synthesis. We saw this in :doc:`/getting_started/example_synth`
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where a design was loaded and elaborated and then went through a series of
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coarse-grain optimizations before being mapped to hard blocks and fine-grain
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cells. Most commands in Yosys will target either coarse-grain representation or
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fine-grain representation, with only a select few compatible with both states.
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Commands such as `proc`, `fsm`, and `memory` rely on the additional information
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in the coarse-grain representation, along with a number of optimizations such as
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`wreduce`, `share`, and `alumacc`. `opt` provides optimizations which are
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useful in both states, while `techmap` is used to convert coarse-grain cells to
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the corresponding fine-grain representation.
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Single-bit cells (logic gates, FFs) as well as LUTs, half-adders, and
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full-adders make up the bulk of the fine-grain representation and are necessary
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for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and
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`memory_map`.
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.. toctree::
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:maxdepth: 3
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synth
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proc
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fsm
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memory
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opt
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techmap_synth
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extract
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abc
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cell_libs
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