Clifford Wolf a7e11261bd Add $specify2 and $specify3 cells to simlib ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2019-04-23 21:36:59 +02:00
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achronix	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
anlogic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
common	Add $specify2 and $specify3 cells to simlib	2019-04-23 21:36:59 +02:00
coolrunner2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
easic	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ecp5	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
gowin	Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master	2019-04-22 09:09:27 +02:00
greenpak4	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
ice40	ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments	2019-04-21 21:40:11 +01:00
intel	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
sf2	Revert "synth_* with -retime option now calls abc with -D 1 as well"	2019-04-18 07:59:16 -07:00
xilinx	Update help message	2019-04-22 11:38:23 -07:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00