mirror of https://github.com/YosysHQ/yosys.git
127 lines
4.4 KiB
Verilog
127 lines
4.4 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
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// > Intel FPGA technology mapping. User must first simulate the generated \
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// > netlist before going to test it on board.
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// Input buffer map
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module \$__inpad (input I, output O);
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cyclonev_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
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endmodule
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// Output buffer map
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module \$__outpad (input I, output O);
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cyclonev_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
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endmodule
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// LUT Map
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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wire VCC;
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wire GND;
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assign {VCC,GND} = {1'b1,1'b0};
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generate
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if (WIDTH == 1) begin
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assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
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end
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else
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if (WIDTH == 2) begin
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cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(VCC),
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.datad(VCC),
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.datae(VCC),
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.dataf(VCC),
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.datag(VCC));
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end
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else
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if(WIDTH == 3) begin
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cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(VCC),
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.datae(VCC),
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.dataf(VCC),
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.datag(VCC));
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end
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else
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if(WIDTH == 4) begin
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cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(VCC),
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.dataf(VCC),
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.datag(VCC));
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end
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else
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if(WIDTH == 5) begin
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cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(VCC),
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.datag(VCC));
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end
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else
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if(WIDTH == 6) begin
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cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
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_TECHMAP_REPLACE_
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(.combout(Y),
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.dataa(A[0]),
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.datab(A[1]),
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.datac(A[2]),
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.datad(A[3]),
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.datae(A[4]),
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.dataf(A[5]),
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.datag(VCC));
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end
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/*else
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if(WIDTH == 7) begin
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TODO: There's not a just 7-input function on Cyclone V, see the following note:
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**Extended LUT Mode**
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Use extended LUT mode to implement a specific set of 7-input functions. The set must
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be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
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[source](Device Interfaces and Integration Basics for Cyclone V Devices).
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end*/
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else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule // lut
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