mirror of https://github.com/YosysHQ/yosys.git
32 lines
1.3 KiB
Plaintext
32 lines
1.3 KiB
Plaintext
read_verilog macc.v
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design -save read
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proc
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hierarchy -top macc
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#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd macc # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:FDRE
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select -assert-count 1 t:DSP48E1
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select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
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design -load read
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proc
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hierarchy -top macc2
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#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd macc2 # Constrain all select calls below inside the top module
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select -assert-count 1 t:BUFG
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select -assert-count 1 t:DSP48E1
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select -assert-count 1 t:FDRE
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select -assert-count 1 t:LUT2
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select -assert-count 41 t:LUT3
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select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D
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