mirror of https://github.com/YosysHQ/yosys.git
f4298b057a
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com> |
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| .. | ||
| Makefile.inc | ||
| cells_sim.v | ||
| lut_sim.v | ||
| pp3_cells_map.v | ||
| pp3_cells_sim.v | ||
| pp3_ffs_map.v | ||
| pp3_latches_map.v | ||
| pp3_lut_map.v | ||
| synth_quicklogic.cc | ||