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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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a582b9d184
yosys
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techlibs
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common
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Clifford Wolf
c69c416d28
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
..
Makefile.inc
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
simcells.v
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
simlib.v
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
stdcells.v
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00