mirror of https://github.com/YosysHQ/yosys.git
168 lines
2.1 KiB
Plaintext
168 lines
2.1 KiB
Plaintext
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bram $__XILINX_RAM16X1D
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init 1
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abits 4
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dbits 1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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bram $__XILINX_RAM32X1D
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init 1
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abits 5
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dbits 1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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bram $__XILINX_RAM64X1D
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init 1
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abits 6
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dbits 1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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bram $__XILINX_RAM128X1D
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init 1
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abits 7
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dbits 1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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bram $__XILINX_RAM32X6SDP
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init 1
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abits 5
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dbits 6
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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bram $__XILINX_RAM64X3SDP
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init 1
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abits 6
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dbits 3
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groups 2
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ports 1 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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bram $__XILINX_RAM32M
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init 1
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abits 5
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dbits 2
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groups 2
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ports 3 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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bram $__XILINX_RAM64M
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init 1
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abits 6
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dbits 1
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groups 2
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ports 3 1
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wrmode 0 1
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enable 0 1
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transp 0 0
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clocks 0 1
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clkpol 0 2
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endbram
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# Disabled for now, pending support for LUT4 arches
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# since on LUT6 arches this occupies same area as
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# a RAM32X1D
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#match $__XILINX_RAM16X1D
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# min bits 2
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# min wports 1
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# make_outreg
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# or_next_if_better
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#endmatch
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match $__XILINX_RAM32X1D
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min bits 3
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min wports 1
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make_outreg
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or_next_if_better
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endmatch
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match $__XILINX_RAM64X1D
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min bits 5
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min wports 1
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make_outreg
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or_next_if_better
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endmatch
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match $__XILINX_RAM128X1D
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min bits 9
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min wports 1
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make_outreg
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or_next_if_better
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endmatch
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match $__XILINX_RAM32X6SDP
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min bits 5
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min wports 1
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make_outreg
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or_next_if_better
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endmatch
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match $__XILINX_RAM64X3SDP
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min bits 6
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min wports 1
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make_outreg
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or_next_if_better
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endmatch
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match $__XILINX_RAM32M
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min bits 5
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min rports 3
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min wports 1
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make_outreg
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or_next_if_better
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endmatch
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match $__XILINX_RAM64M
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min bits 5
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min rports 3
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min wports 1
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make_outreg
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endmatch
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